HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 18

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
15 - 10
7 - 0
9 - 8
7 - 0
7 - 0
7 - 0
BIT
BIT
BIT
BIT
BIT
Horizontal Drive
Programmable End
Time
Not Used
Horizontal Drive
Programmable End
Time
Phase Locked Loop
Filter Adjust Test
Register
Phase Locked Loop
Horizontal Sync
Detect Window
DC Restore
Programmable Start
Time
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
TABLE 23. PHASE LOCKED LOOP SYNC DETECT WINDOW REGISTER
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
Write Ignored, Read 0’s
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
The Phase Locked Loop time constants can be changed for testing purposes. It is rec-
ommended that the default value of (20
These bits control the PLL horizontal sync detect window. This window sets the length
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs. For NTSC this value should be DD
This register provides a programmable delay for the internal DC RES signal. The start
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
TABLE 22. PHASE LOCKED LOOP ADJUST REGISTER
TABLE 20. HORIZONTAL SYNC END TIME REGISTER
TABLE 21. HORIZONTAL SYNC END TIME REGISTER
TABLE 24. DC RESTORE START TIME REGISTER
DESTINATION ADDRESS = 0E
DESTINATION ADDRESS = 0F
DESTINATION ADDRESS = 10
DESTINATION ADDRESS = 11
DESTINATION ADDRESS = 12
HMP8112
18
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
) always be used. The reset state is 00
H
H
H
H
H
H
and for PAL, FF
H
.
H
.
0010 0000
0000 0000
1101 1101
0011 0111
XXXX XX
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
00
B
B
B
B
B