A6850 ALTERA [Altera Corporation], A6850 Datasheet
A6850
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A6850 Summary of contents
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... September 1996, ver. 1 Features General The a6850 MegaCore function implements an ACIA, which is a universal asynchronous receiver/transmitter (UART). The a6850 provides an Description interface between a microprocessor and a serial communications channel. The a6850 receives and transmits data in a variety of configurations, including 7- or 8-bit data words, with odd, even parity, and stop bits ...
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... Output txdata Output do[7..0] 82 Table 1 describes the input and output ports of the a6850. Polarity Low Clear to send, a modem signal name. The ncts input inhibits the assertion of the transmit data register empty (tdre) status bit. Low Data carrier detect, a modem signal name. When the ndcd signal transitions from low to high, an interrupt to the microprocessor is generated ...
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... Description Figure 2. a6850 Block Diagram Bus rnw Interface Contro rs nirq 8 do Altera Corporation a6850 Asynchronous Communications Interface Adapter Data Sheet Figure 2 shows the a6850 block diagram. Transmitter 8 Data Register Control Register Status Register 8 8 Receiver Data 8 Register Registers ...
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... Asynchronous Communications Interface Adapter Data Sheet 84 Transmitter Data Register The transmitter data register (TDR) is written to by the microprocessor or other controlling device. Once the existing data bits in the output shift register are completely transmitted out, the TDR transfers new data into the output shift register ...
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... Master reset. When master reset is selected, the a6850 is reset to a known state; the status register is cleared, and the transmit and receive operations are halted and initialized. Table 4. Word Select Bits ...
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... Asynchronous Communications Interface Adapter Data Sheet 86 Transmitter Control Bits 5 and 6 of the control register are the tc bits, (see are responsible for: Enabling or disabling the interrupt caused by a transmitter data register empty (tdre) condition. Controlling the request to send (nrts) signal. Transmitting a break character on the txdata output. ...
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... Bit 1 of the status register is the tdre bit. When high, the tdre bit indicates that data has been transferred from the transmitter data register to the output shift register. At this point, the a6850 is ready to accept a new transmit data byte. However, if the ncts signal is high, the tdre bit remains low regardless of the status of the transmitter data register ...
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... Asynchronous Communications Interface Adapter Data Sheet 88 Framing Error Bit 4 of the status register is the fe bit. The fe bit is asserted when a received character does not end with the specified stop bit, which is usually caused by a transmission error. The fe bit is set when the received character is transferred to the receiver data register, and remains set until another character is written to the receiver data register ...
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... The microprocessor interfaces with the a6850 when the cs input is set to a logic 110 and the rnw input is set to a logic low when writing logic high when reading. The rs input then chooses the appropriate register ...
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... Receive data register transfer Start Bit Detection The a6850 begins receiving data when a start bit is detected. A start bit is a logic low over the rxdata input, and is sampled on each rising edge of the rxclk signal. Once the a6850 detects a logic low, it begins counting the logic low samples according to the specified divide-by mode (i ...
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... Start Bit Start Bit Parity & Stop Bit Detection The a6850 counts the number of data bits as it shifts. When the number of data bits received matches the number specified in the control register, the a6850 expects either a parity bit or a stop bit. If parity is enabled, the a6850 samples for the parity bit, which is then processed for parity ...
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... Asynchronous Communications Interface Adapter Data Sheet 92 The a6850 receives data with one or two stop bits. If one stop bit is specified in the control register, the a6850 will expect one stop bit before starting the synchronization process. Similarly, if two stop bits are specified, the synchronization process begins after detecting two stop bits. ...
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... Altera Corporation a6850 Asynchronous Communications Interface Adapter Data Sheet Transmit Start Bit After data is transferred to the output shift register, a start bit (i.e., logic low) is placed on the txdata output on the falling edge of txclk. The start bit stays active for the number of clock cycles specified by the divide-by mode (i ...
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... The following characteristics distinguish the Altera Motorola MC6850 device: The a6850 has separate input and output data buses, while the MC6850 device has a single tri-state data bus. The nreset (asychronous reset) input on the a6850 is not available in the Motorola MC6850 device. ...
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