A6850 ALTERA [Altera Corporation], A6850 Datasheet - Page 14

• Manufacturer Part Number: A6850
• Description: Asynchronous Communications Interface Adapter
• Manufacturer: ALTERA [Altera Corporation]

a6850 Asynchronous Communications Interface Adapter Data Sheet
Variations &
Clarifications
94
The transmit operation produces an interrupt (i.e., logic low on
nirq) when the following conditions all occur:
The receive operation produces an interrupt when the following
conditions occur:
Reset Operation
The a6850 is reset in one of two ways:
The nreset input is used as an asynchronous clear to all internal
registers. Placing the a6850 into master reset will synchronously
clear the registers. However, master reset only works if both clocks
are running.
The following characteristics distinguish the Altera
Motorola MC6850 device:
Transmit interrupts are enabled.
The tdre flag is set.
The ncts signal is low.
Receive interrupts are enabled (i.e., the rie control signal is
high).
Any one of the following signals is set: rdrf, ovr, or ndcd.
Driving the nreset input low.
Writing logic 1s into the cds bits of the control register.
The a6850 has separate input and output data buses, while the
MC6850 device has a single tri-state data bus.
The nreset (asychronous reset) input on the a6850 is not
available in the Motorola MC6850 device.
The a6850 bus interface was designed using synchronous
design techniques, allowing it to operate using various part
designations, speed grades, and optimization techniques.
The a6850 requires that the txclk signal is always connected
to a free running clock, and that the e signal is high for at least
one txclk clock cycle when reading and writing data.
Altera Corporation
®
a6850 from the