STPM11_08 STMICROELECTRONICS [STMicroelectronics], STPM11_08 Datasheet - Page 17

• Manufacturer Part Number: STPM11_08
• Description: Single phase energy metering IC with pulsed output and digital calibration
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 15. First order ∑ Δ A/D Converter
7.4
f
output is subtracted from the input signal. If the loop gain is high enough, the average value
of the DAC output (and therefore the bit stream) can approach that of the input signal level.
When a large number of samples are averaged, a very precise value of the analog signal is
obtained. This averaging is carried out in the DSP section which implements decimation,
integration and DC offset cancellation of the supplied ∑ Δ signals. The gain of the decimation
filters is 1.004 for the voltage channel and 0.502 for the current channel. The resulting signal
has a resolution of 11bits for voltage channel and 16 bits for current channel.
Period and line voltage measurement
The period module measures the period of base frequency of voltage channel and checks if
the voltage signal frequency is in the band from f
produced at every positive peak of the line voltage. If the counted number of pulses between
two trailing edges of this signal is higher than the f
counting is stopped (internal signal is not available), it means that the base frequency is
lower than f
If the counted number of pulses within one line period is higher than the f
pulses, the base frequency exceeds the limit. In this case, such error must be repeated
three times in a row, in order to set the error flag BFR.
The BFR flag is also set if the value of the RMS voltage drops below a certain value (BFR-
on) and it is cleared when the RMS voltage goes above BFR-off threshold. The table below
shows the equivalent RMS voltage on the V
channel calibrator.
The BFR flag is also set if the RMS voltage across V
calculated with the following formula:
(CT/Shunt)
V
CLK
IRMS
/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC
−
BFR
Input analog signal
=
CLK
6703
/2
64
17
⋅
Hz and an internal error flag BFR (Base Frequency Range) is set.
K
+
V
Σ
-
Integrator
∫
DAC
f
IP
CLK
/V
/4
IN
CLK
pins according to the value of the voltage
CLK
/2
IP
/2
17
-V
17
Output digital signal
IN
to f
Hz equivalent pulses or if the
drops below a threshold value
CLK
/2
15
. An internal signal is
CLK
/2
15
equivalent
17/45