ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet - Page 26

• Manufacturer Part Number: ADUC702X_1
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC will convert the analog input and provide a
12-bit result in the ADC data register.
The top 4 bits are the sign bits and the 12-bit result is placed
from bit 16 to 27 as shown in Figure 10. Again, it should be
noted that in fully differential mode, the result is represented in
two’s complement format, and in pseudo differential and single-
ended mode, the result is represented in straight binary format.
SIGN BITS
The same format is used in DACxDAT, simplifying the software.
1111 1111 1111
0111 1111 1111
0111 1111 1110
0111 1111 1101
0000 0000 0001
0000 0000 0000
1000 0000 0010
1000 0000 0001
1000 0000 0000
Bit
7
6
5
4-3
2-0
31
OUTPUT
CODE
Description
Enable Conversion
Set by the user to enable conversion mode
Cleared by the user to disable conversion mode
Enable ADC
Set by the user to enable the ADC
Cleared by the user to disable the ADC
ADC power control:
Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert
correctly.
Cleared by the user to place the ADC in power-down mode
Conversion Mode:
00
01
10
11
Conversion Type:
Figure 9: ADC transfer function in differential mode
-V
1LSB =
REF
Single Ended Mode
Differential Mode
Pseudo-Differential Mode
Reserved
27
+ 1LSB
VOLTAGE INPUT (Vin+ - Vin-)
Figure 10: ADC Result Format
2xV
BUSY
4096
REF
0LSB
12-bit ADC RESULT
+V
BUSY
REF
Table 7: ADCCON MMR Bit Designations
pin
- 1LSB
BUSY
pin
16
Rev. PrA | Page 26 of 78
15
0
ADC MMRS interface
The ADC is controlled and configured via a number of MMRs
that are listed below and described in detail in the following
pages:
- ADCCON: ADC Control Register allows the programmer to
- ADCCP: ADC positive Channel selection Register
- ADCCN: ADC negative Channel selection Register
- ADCRST: ADC Reset Register. Resets all the ADC registers
- ADCOF: Offset calibration register. 10-bit register
- ADCGN: Gain calibration register. 10-bit register
enable the ADC peripheral, to select the mode of operation of
the ADC, either Single-ended, pseudo-differential or fully
differential mode and the conversion type. This MMR is
described Table 7.
ADCSTA: ADC Status Register, indicates when an ADC
conversion result is ready. The ADCSTA register contains
only one bit, bit (bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion generating an
ADC interrupt, it is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the
ADCBusy pin. This pin is high during a conversion. When
the conversion is finished, ADCBusy goes back low. This
information can be available on P0.3 (see chapter on GPIO) if
enabled in ADCCON register.
ADCDAT: ADC Data Result Register, hold the 12-bit ADC
result as shown Figure 10
to their default value.
Preliminary Technical Data