ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet - Page 69

• Manufacturer Part Number: ADUC702X_1
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
External Memory Interfacing
The only ADuC702x models which feature an external memory
interface are the ADuC7026 and ADuC7027. The external
memory interface requires a larger number of pins, this is why it
is only available on larger pin count package.
The pins required for interfacing to an external memory are:
Pin
AD[15:0}
A16
MS[3:0}
WR
RS
AE
BHE, BLE
There are four external memory regions available. These are
XMxCON
Bit
1
0
XMxPAR
Bit
15
14-12
11
10
9
Description
Selects between 8 and 16 bit data bus width.
Set by the user to select a 16 bit data bus
Cleared by the user to select an 8 bit data bus.
Enables Memory Region
Set by the user to enable memory region
Cleared by the user to disable the memory region
Description
Enable Byte write strobe
Set by the user gates the BHE and BLE outputs with the WR output. This allows byte write capability without using
Number of wait states on the Address latch enable strobe.
Enable dynamic addressing
Set by the user to enable 16 bit addressing mode
Cleared by the user to enable 8 bit addressing mode
Extra address hold time
Set by the user to disable extra hold time
Cleared by the user to enable one clock cycle of hold on address in read and write
Extra bus transition time on Read
Set by the user to disable extra bus transition time
Function
Address/Data Bus
Extended Addressing
Memory Select Pins
Write Strobe
Read Strobe
Address Latch Enable
Byte Write Capability
Rev. PrA | Page 69 of 78
documented in the table below.
Address Start
0x10000000
0x20000000
0x30000000
0x40000000
Each external memory region can be controlled through the
following three MMRs
XMCFG is set to 1 to enable external memory access. This
must be set to 1 before any port pins will function as external
memory access pins. The port pins must also be individually
enabled via the GPxCON MMR
XMxCON are registers that enable/disable a memory region.
This register also controls the data bus width of the memory
region.
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Address End
0x1001FFFF
0x2001FFFF
0x3001FFFF
0x4001FFFF
ADuC702x Series
Contents
External Memory 0
External Memory 1
External Memory 2
External Memory 3