DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 12

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DDR2 Memory Controller for PowerPC 440 Processors
12
Design Implementation
Top-Level Design
The PPC440MC DDR2 Memory Controller is comprised of the controller, the physical layer, and the
FIFO interface as shown in
X-Ref Target - Figure 3
Physical Layer
The physical layer is comprised of the write datapath, the read datapath, the calibration state machine
for DQS and DQ calibration, the calibration logic for read enable alignment, and the memory
initialization state machine. The write datapath generates the data and strobe signals transmitted
during a Write command. The read datapath captures the read data in the read strobe domain.
Write Datapath
The write datapath, shown in
Two data words are presented on the rising edge of the FPGA clock and the ODDR converts it into DDR
data.
X-Ref Target - Figure 4
Write Data Rise
Write Data Fall
FPGA Clock
Physical Layer
Figure 3: PPC440MC DDR2 Memory Controller Block Diagram
Read/Write
Controller
FIFO
Figure
Figure
3.
D1
D2
4, is implemented using the IOB ODDR in the same edge mode.
Figure 4: Write Datapath
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DDR2 SDRAM
Clock, Reset,
I/O Control
MC_TOP
ODDR
DS567 (v1.1.1) March 31, 2008
MCI
DS567_03_030608
ds567_04_022708
DQ