DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 4

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DDR2 Memory Controller for PowerPC 440 Processors
4
PPC440MC DDR2 Memory Controller Design Parameters
To create a uniquely tailored PPC440MC DDR2 Memory Controller, certain parameterizable features in
the PPC440MC DDR2 Memory Controller design allow a design that only utilizes the resources
required by the system and runs at the best possible performance.
features in the PPC440MC DDR2 Memory Controller.
Table 2: PPC440MC DDR2 Memory Controller Design Parameters
Target FPGA family
Base Address for Memory
High Address for Memory
CPMINTERCONNECTCLK to
PPC440MC DDR2 clock ratio
DDR2 clock period (t
MCI data width
Number of generated clock pairs
supplied to the DDR2 memory
Supported number of external DDR2
memory banks
Include ECC Logic
DDR2 Data Width
DDR2 Strobe Width
DDR2 Data Mask Width
DDR2 Row Address Width
DDR2 Column Address Width
DDR2 Bank Address Width
DDR2 CAS Latency
DDR2 Burst Length
DDR2 is a registered DIMM
On Die Termination Selection
DDR2 ODT Width
DDR2 Additive Latency
Delay after ACTIVE command before
READ/WRITE command (ps)
Feature/Description
CK
) in ps
PPC440MC DDR2 Memory Controller Features
C_FAMILY
C_MEM_BASEADDR
C_MEM_HIGHADDR
C_MIB_MC_CLOCK_RATIO
C_MC_MIBCLK_PERIOD_PS
C_MIBDATA_WIDTH
C_NUM_CLK_PAIRS
C_NUM_RANKS_MEM
C_INCLUDE_ECC_SUPPORT 0 = Disable
C_DDR_DWIDTH
C_DDR_DQS_WIDTH
C_DDR_DM_WIDTH
C_DDR_RAWIDTH
C_DDR_CAWIDTH
C_DDR_BAWIDTH
C_DDR_CAS_LAT
C_DDR_BURST_LENGTH
C_REG_DIMM
C_DDR2_ODT_SETTING
C_DDR2_ODT_WIDTH
C_DDR2_ADDT_LAT
C_DDR_TRCD
Parameter Name
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DDR2 Features
(1)
(2)
(3)
0 or 1 for 1:1, 2:1, or
3:1clock ratios
2 for 3:2 clock ratio
3000 to 8000
128
1, 2, 4
1, 2, 4
1 = Enable
16, 32, 64, 72
2, 4, 8, 9
2, 4, 8, 9
All supported memory row
address widths
All supported memory column
address widths
2, 3
3, 4, 5
4, 8
0 = Unbuffered memory
1 = Registered memory
0 = Disables ODT
1 = ODT enabled, R
2 = ODT enabled, R
3 = ODT enabled, R
0 to 4
0 to 4
Table 2
Allowable Values
DS567 (v1.1.1) March 31, 2008
lists the parameterizable
TT
TT
TT
= 150Ω
= 75Ω
= 50Ω
0
3000
128
1
1
0
64
8
8
14
10
2
5
4
1
1
1
0
15000
Default
Value