PCI9656-BA66BIG PLX [PLX Technology], PCI9656-BA66BIG Datasheet



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PLX [PLX Technology]

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V E R S I O N 1 . 0
C o n n e c t i v i t y
P e r f o r m a n c e
C o n t r o l
64-bit, 66MHz PCI r2.2 compliant
Motorola PowerQUICC and
generic 32-bit, 66MHz local
bus modes
3.3V I/O, 5V tolerant bus
PICMG 2.1 r2.0 Hot Swap Silicon
272-ball, 27 x 27 mm, 1.27 mm
pitch PBGA
Zero wait state burst operation
PCI bus bursts to 528 MB/sec
Local bus bursts to 264 MB/sec
2 DMA Channels
Block and Scatter/Gather transfers
DMA descriptor ring management
Demand Mode and EOT
Hardware controls
Direct Master data transfers
Generate any PCI transaction
Read ahead and programmable
read prefetch counter
Direct Slave data transfers
Access 8-, 16-, and 32-bit local
bus devices
Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
I 2 O r1.5 messaging unit
Eight mailbox and two
doorbell registers
PCI arbiter supports 7
external masters
Host mode reset/interrupt signal
Event (PME) generation support
Serial EEPROM interface
JTAG boundary scan
Power Management
2 0 0 2
64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
Maximum PCI Bandwidth for Your 32-bit Local Bus Applications
The PCI 9656 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection
to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its
Data Pipe Architecture™ technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-
ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.
The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI
I/O with those devices.
M o v e Y o u r 3 2 - b i t L o c a l B u s D e s i g n s U p t o
6 4 - b i t , 6 6 M H z P C I O p e r a t i o n
As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX
continues to provide leading edge, high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of
enhancements for the needs of today's telecom, networking, and I/O adapter designs:
The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.
64-bit, 66MHz PCI operation
32-bit, 66MHz local bus operation
Dynamic DMA descriptor ring management with Valid bit semaphore control
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit
Initialization, and Intially Not Responding Support
PCI Power Management r1.1 D3
PCI arbiter supporting 7 external masters
Reset and interrupt pins configurable for embedded host applications
JTAG boundary scan
PCI 9656
MPC 850/860 PowerQUICC Designs
& Generic 32-bit, 66MHz Local Bus Design s
Power Management Event (PME) generation

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PCI9656-BA66BIG Summary of contents

Page 1

64-bit, 66MHz PCI r2.2 compliant Motorola PowerQUICC and generic 32-bit, 66MHz local bus modes ...

Page 2

The PCI 9656 64-bit, 66MHz PCI I/O accelera- tor is the most advanced, general-purpose bus mastering device available for Motorola MPC 850/860 PowerQUICC and generic ...

Page 3

Motorola PowerQUICC Designs The PCI 9656 is ideal for MPC 850/860-based PowerQUICC designs. Targeted datacom and telecom applications include high-speed routers/switches, ...

Page 4

PCI Bus Interface Control Logic minimize risk and lower your product development costs, PLX o ers ...

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