PCI9656-BA66BIG PLX [PLX Technology], PCI9656-BA66BIG Datasheet - Page 2

• Manufacturer Part Number: PCI9656-BA66BIG
• Manufacturer: PLX [PLX Technology]

P C I 9 6 5 6 F e a t u r e s
The PCI 9656 64-bit, 66MHz PCI I/O accelera-
tor is the most advanced, general-purpose
bus mastering device available for Motorola
MPC 850/860 PowerQUICC and generic
32-bit, 66MHz local bus based designs. The
PCI 9656 incorporates PLX’s industry leading
Data Pipe Architecture technology, featuring
DMA engines, programmable Direct Master
and Direct Slave data transfer modes, and PCI
messaging functions.
I n t e r f a c e s
PCI
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Local Bus
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64-bit, 66MHz r2.2 operation
Zero wait state bursts to 528 MB/s
Dual Address Cycle (DAC) support as a
PCI bus master
Vital Product Data (VPD)
3.3V I/O, 5V tolerant
PICMG 2.1 r2.0 Hot Swap Silicon
Programming Interface 0 (P=0)
Bias Voltage Support
Early Power Support
Initially Not Responding Support
PCI Hot Plug r1.0
PCI Power Management r1.1
Supports D0, D1, D2, D3
power states
D3
generation to meet PC 2001 Windows
98/2000 communication adapter logo
certification requirements
Three local bus options on the device
M Mode: Motorola MPC 850/860
PowerQUICC and PowerPC 80x/82x
C Mode: De-multiplexed address and data
buses for Intel i960
and FPGAs, and others
J Mode: Multiplexed address and data
buses for Intel i960, IBM PowerPC 401, IDT
RC32364, DSPs, IOP 480, and others
32-bit, 66MHz operation
Zero wait state bursts to 264 MB/s
3.3V I/O, 5V tolerant
Asynchronous clock inputs to PCI
and local bus
COLD
Power Management Event (PME)
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, DSPs, custom ASICs
HOT
, & D3
COLD
Serial EEPROM
D a t a P i p e A r c h i t e c t u r e
DMA
Service DMA descriptors, mastering on both
bus interfaces during data transfer
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Direct Master
Service local bus masters by mastering on
the PCI bus
Direct Slave
Service PCI bus masters by mastering on the
local bus
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Store configuration register power on,
reset values
An alternative to expansion ROM for stor-
ing Vital Product Data (VPD)
Supports 2 Kbit/4 Kbit microwire devices
with sequential read
Two independent channels provide flexible
prioritization scheme
Each channel has its own bi-directional
32 Qword (256 byte) deep FIFO
Block Mode services a single DMA
descriptor in PCI 9656 registers
Scatter/Gather Mode services DMA
descriptor linked lists in memory
Burst descriptors from PCI or local
bus memory
Descriptor lists either linear (static) or
circular (dynamic) with Valid bit sema-
phore control
Direct Hardware DMA controls
Demand Mode to pause/resume
End of Transfer (EOT) to abort
Programmable local bus burst length,
including infinite
Enhanced M Mode supports bursts beyond
PowerQUICC 16 byte limit
Two local bus address spaces map to PCI
bus: one to memory; one to I/O
Generate all PCI memory and I/O
transaction types, including Memory
Write and Invalidate (MWI)
Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
Read ahead and programmable read
prefetch counter
PowerQUICC deferred reads and IDMA
(M mode only)
Two general-purpose and one expansion
ROM PCI address spaces map to local
bus memory
Each address space may specify 8-, 16-,
or 32-bit local bus data transfer
Advanced Performance Features Common to
DMA, Direct Master, and Direct Slave
Messaging
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E m b e d d e d H o s t F e a t u r e s
P a c k a g e
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B a c k w a r d C o m p a t i b i l i t y
R e l a t e d P L X P r o d u c t s
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Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
Deferred reads, deferred writes, posted
writes, read ahead, and programmable read
prefetch counter
Programmable #READY time out
and recovery
Zero wait state PCI & local bus bursts
Deep FIFOs prolong bursts
Unaligned PCI and local bus transfers of
any byte length
On-the-fly Endian conversion
Programmable local bus wait states
Parity checking on both buses
Provides industry standard I 2 O r1.5
messaging unit
Supports general-purpose messaging
for proprietary message schemes
Eight 32-bit mailbox registers for polled
environments
Two 32-bit doorbell register for interrupt
driven environments
PCI arbiter supports 7 external masters
Reset and interrupt signals configurable for
embedded host operation
Type 0/1 Configuration support allows
local bus master to configure PCI bus
and devices
272-pin PBGA
27 mm x 27 mm, 1.27 mm ball pitch
Low power 2.5V CMOS core
3.3V I/O, 5V tolerant
Industrial temperature range operation
IEEE 1149.1 JTAG boundary scan
The PCI 9656 register set is backward
compatible with the PCI 9054, with new
registers added for the new functionality
enhancements
Support for 32-bit, 66MHz PCI with 32-bit,
66MHz C, J, and M Local Bus support is
provided by the PCI 9056
See the PCI 9056 product brief for details