AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet

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AD9397/PCB

Manufacturer Part Number
AD9397/PCB
Description
DVI Display Interface
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
DVI interface
Digital video interface
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9397 is a digital visual interface (DVI) receiver
integrated on a single chip. Also included is support for high
bandwidth digital content protection (HDCP) with internal key
storage.
The AD9397 contains a DVI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can receive encrypted
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(HDCP 1.1)
Supports high-bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
DVI 1.0
150 MHz DVI receiver
Supports high-bandwidth digital content protection
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
DDCSDA
video content. The AD9397 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9397 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
DDCSCL
RTERM
RxC+
RxC–
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
MDA
SDA
MCL
SCL
FUNCTIONAL BLOCK DIAGRAM
POWER MANAGEMENT
SERIAL REGISTER
DVI RECEIVER
DVI Display Interface
DIGITAL INTERFACE
HDCP
AND
© 2005 Analog Devices, Inc. All rights reserved.
Figure 1.
2
R/G/B 8 × 3
OR YCbCr
DATACK
DE
HSYNC
VSYNC
AD9397
AD9397
www.analog.com
2
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
DE
DATACK
HSOUT
VSOUT
SOGOUT

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AD9397/PCB Summary of contents

Page 1

FEATURES DVI interface Supports high-bandwidth digital content protection RGB to YCbCr 2-way color conversion 1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats Digital video interface DVI 1.0 150 MHz DVI receiver Supports high-bandwidth digital content ...

Page 2

AD9397 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Digital Interface Electrical Characteristics ............................... 4 Absolute Maximum Ratings............................................................ 6 Explanation of Test ...

Page 3

SPECIFICATIONS ELECTRICAL CHARACTERISTICS 3 1.8 V, ADC clock = maximum Table 1. Parameter Temp RESOLUTION Data-to-Clock Skew Full Serial Port Timing t Full BUFF t Full STAH ...

Page 4

AD9397 DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS 3 1.8 V, ADC clock = maximum Table 2. Parameter RESOLUTION DC DIGITAL I/O SPECIFICATIONS High Level Input Voltage ...

Page 5

Parameter AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (T ) DPS Channel to Channel Differential Input Skew (T ) CCS Low-to-High Transition Time for Data and Controls (D ) LHT Low-to-High Transition Time for DATACK (D ) LHT ...

Page 6

AD9397 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 12 BLUE ...

Page 8

AD9397 Pin Type Pin No. POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL 83 82 HDCP DATA ENABLE 88 RTERM 46 Table 6. Pin Function Descriptions ...

Page 9

Pin Description DATA OUTPUTS RED [7:0] Data Output, Red Channel. GREEN [7:0] Data Output, Green Channel. BLUE [7:0] Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is ...

Page 10

AD9397 DESIGN GUIDE GENERAL DESCRIPTION The AD9397 is a fully integrated digital visual interface (DVI ) for receiving RGB or YUV signals for display on flat panel monitors, projectors or PDPs. This interface is capable of decoding HDCP-encrypted signals through ...

Page 11

TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. Figure 3 shows the timing operation of the AD9397. t PER t ...

Page 12

AD9397 4:4:4 TO 4:2:2 FILTER The AD9397 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color ...

Page 13

SERIAL REGISTER MAP The AD9397 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 10. ...

Page 14

AD9397 Hex Read/Write Default Address or Read Only Bits Value [4] * **1**** [0] * ******0 0x25 Read/Write [7 :6] 0 1****** [5:4] * *11**** [3:2] * ***00** [1] * *****1* [0] *******0 0x26 Read/Write [7] 0******* [5] **0***** [4] ...

Page 15

Hex Read/Write Default Address or Read Only Bits Value 0x28 Read/Write [7 :2] 0 11000** [1:0] ******01 0x29 Read/Write [7:0] 00000100 0x2A Read/Write [3:0] ****0101 0x2B Read/Write [7:0] 00000000 0x2C Read/Write [3:0] ****0010 0x2D Read/Write [7:0] 11010000 0x2E Read/Write [7] ...

Page 16

AD9397 Hex Read/Write Default Address or Read Only Bits Value 0x36 Read/Write [7 :0] 0 1010010 0x37 Read/Write [4 :0] * **01000 0x38 Read/Write [7:0] 00000000 0x39 Read/Write [4 :0] * **00000 0x3A Read/Write [7:0] 00000000 0x3B Read/Write [4 :0] ...

Page 17

Hex Read/Write Default Address or Read Only Bits Value 0x49 Read/Write [4:0] ***01110 0x4A Read/Write [7:0] 10000111 0x4B Read/Write [4:0] ***11000 0x4C Read/Write [7:0] 10111101 0x50 Read/Write [7:0] 00100000 0x56 Read/Write [7:0] 00001111 0x59 Read/Write [6] [5] [4] [0] Register ...

Page 18

AD9397 2-WIRE SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bit[7:0] Chip Revision An 8-bit value that reflects the current chip revision. 0x11—Bit[7] HSYNC Source 0 = HSYNC SOG. The power-up default is 0. These selections are ignored if Register ...

Page 19

HSYNC Duration An 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9397 then counts a number of pixel ...

Page 20

AD9397 0x26—Bit[7] Output Three-State When enabled, this bit puts all outputs (except SOGOUT high impedance state normal outputs all outputs (except SOGOUT) in high impedance mode. The power-up default setting is 0. 0x26—Bit[3] Power-Down ...

Page 21

DVI Content Encrypted This read-only bit is high when HDCP decryption is in use (content is protected). The signal goes low when HDCP is not being used. Customers can use this bit to allow copying of the content. The ...

Page 22

AD9397 0x35—Bits[4:0] Color Space Conversion Coefficient A1 MSBs These 5 bits form the 5 MSBs of the Color Space Conversion Coefficient A1. This combined with the 8 LSBs of the following register form a 13-bit, twos complement coefficient which is ...

Page 23

SERIAL CONTROL PORT A 2-wire serial interface control interface is provided in the AD9397 two AD9397 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface comprises ...

Page 24

AD9397 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control ...

Page 25

PCB LAYOUT RECOMMENDATIONS The AD9397 is a high precision, high speed digital device. To achieve the maximum performance from the part impor- tant to have a well laid-out board. The following is a guide for designing a board ...

Page 26

AD9397 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 16. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9397) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x2C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E ...

Page 27

Table 20. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 Value ...

Page 28

... ORDERING GUIDE Max Speeds (MHz) Model Analog Digital 1 AD9397KSTZ-100 100 100 1 AD9397KSTZ-150 150 150 AD9397/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05691-0-10/05(0) 1.60 MAX BSC SQ 0.75 100 1 0.60 0.45 PIN 1 ...

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