AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 15

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

Hex
Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
[6]
Bits
[7
[1:0]
[7:0]
[3:0]
[7:0]
[3:0]
[7:0]
[7]
[5]
[3]
[2:0]
[6]
[5]
[4]
[7:4
[3:0]
[7]
[6]
[5:0]
[7]
[6]
[5:0]
[7:6]
[5]
[4]
[3]
[2]
[1]
[6:5]
[4:0]
:2]
]
Default
Value
0
******01
00000100
****0101
00000000
****0010
11010000
0*******
*0******
**0*****
****0***
*****000
*0******
**0*****
***0****
1001****
****0110
0*******
*0******
**001101
1*******
*
*
10******
**0*****
***0****
****0***
*
******0*
*01* ****
*
0******
*010101
****0**
**01100
11000**
Register Name
V
HS Delay MSB
HS Delay
Line Width MSB
Line Width
Screen Height MSB
Screen Height
Test 1
TMDS Sync Detect
TMDS Active
HDCP Keys Read
DVI Quality
DVI Content
Encrypted
DVI HSYNC Polarity
DVI VSYNC Polarity
MV Pulse Max
MV Pulse Min
MV Oversample En
MV Pal En
MV Line Co
MV Detect Mode
M
M
MV Pulse Limit Set
Low Freq Mode
Low Freq Override
Up Conversion Mode
C
CSC_Enable
CSC_Mode
C
S Delay
rCb Filter Enable
SC_Coeff_A1 MSB
V Settings Override
V Line Count End
Rev. 0 | Page 15 of 28
unt Start
MSB, Register 0x2B.
Detects a TMDS DE.
Detects a TMDS clock.
Tells the Macrovision d
Sets the start line for Macrovision detection.
Sets the end line for Macrovision det
Description
S
of active video.
MSB, Register 0x
Sets the delay (in pix
start of active video.
Sets the width of the active video line in pixels.
MSB, Register 0x2D.
Sets the height of the active screen in lines.
Must be written to 1 for proper operation.
Returns 1 when read of
Returns quality number based on DE edges.
This bit is high when HDCP decryption is in u
protected). The signal goes low when HDCP is not being use
Customers can use this bit to determine whether to allow
copying of the content. The bit should be sampled at regul
intervals because it can change on a frame-by-frame basis.
Returns DVI HSYNC polarity.
Returns DVI VSYNC polarity.
Sets the maximum pseudo sy
detection.
Sets the mi
detection.
Tells the Ma
oversampling or not.
0 = standard definition.
1 = progressive scan mode.
0 = use hard-coded settings
1 = use I
Sets the number of pulses required in the las
only).
Sets au
should only be set for pixel clocks <80 MHz.
Allows the previous bit to be used to set low
rather than the internal auto-detect.
0 = repeat Cr and Cb values.
1 = interpolate Cr and Cb values.
Enables the FIR filter for 4:2:2 CrCb
Enables the color space converter (CSC). The default settings for
the CSC provide HDTV-to-RGB conversion.
Sets the fixed point position of the CSC coef
the A4, B4, and C4 offsets.
00 = ±1.0, −4096 to +4095.
01 =±2.0, −8192 to +8190.
1× = ±4.0, −16384 to +16380.
MSB, Register 0x36.
ets the delay (in lines) from the VSYNC leading edge to the start
dio PLL to low frequency mode. Low frequency mode
2
C values for these settings.
nimum pseudo sync pulse width for Macrovision®
crovision detection engine whether we are
29.
els) from the HSYNC leading edge to the
etection engine to enter PAL mode.
EEPROM keys is successful.
for line counts and pulse widths.
nc pulse width for Macrovision
output.
ection.
ficients, including
t 3 lines (SD mode
se (content is
frequency mode
AD9397
ar
d.