ADV3201 AD [Analog Devices], ADV3201 Datasheet

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... SWITCHES Figure 1. an output bus if building a larger array. The part is available in a gain of +1 (ADV3200 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled ...

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... Pin Configuration and Function Descriptions ............................. 8 Truth Table and Logic Diagram ............................................... 11 REVISION HISTORY 10/08—Revision 0: Initial Version   I/O Schematics ................................................................................ 12   Typical Performance Characteristics ........................................... 13   ADV3200 ..................................................................................... 13   ADV3201 ..................................................................................... 20   Theory of Operation ...................................................................... 27   Applications Information .............................................................. 29   Programming .............................................................................. 29   AC Coupling of Inputs .............................................................. 29   On-Screen Display (OSD) ......................................................... 31   ...

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... ADV3201 DC, disabled Output Capacitance Disabled Output Voltage Range ADV3200 ADV3201 No output load INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range ADV3200 ADV3201 No output load = 25° (ADV3200 (ADV3201 Min = 150 Ω kΩ 150 Ω kΩ L 900 3.2 −1.1 to +1.1 − ...

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... ADV3201 Differential Phase Error ADV3200 ADV3201 Input Voltage Noise ADV3200 ADV3201 Min 1 0.1 = VCLAMP + 0.1 V −2.9 = VCLAMP − 0 25° (ADV3200 (ADV3201 Test Conditions/Comments Min 200 mV p p-p 200 mV p p-p 0.1 dB, 200 mV p-p 0.1 dB p-p 1 step 2 V step, peak NTSC or PAL NTSC or PAL 0 ...

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... LOAD DATA INTO SERIAL REGISTER ON RISING EDGE 3 OUT31 (D5 Figure 2. Timing Diagram, Serial Mode Rev Page ADV3200/ADV3201 Min Typ Max ±0.1 ±2.3 ±0.1 ±2.7 ±0.1 ±2.2 ±0.1 ±2.7 ±5 ±30 −10 − Limit Min ...

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... ADV3200/ADV3201 CLK DATA IN UPDATE Table 4. Logic Levels, DVCC = 3 RESET, CS, RESET, CS, DATA OUT CLK, DATA IN, CLK, DATA IN, UPDATE, OSDS UPDATE, OSDS 2.5 V min 0.8 V max 2.7 V min INCREASING TIME Figure 3. Programming Example ...

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... Package Type 176-Lead LQFP_EP POWER DISSIPATION The ADV3200/ADV3201 are operated with ±2 ±3.3 V supplies and can drive loads down to 150 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken to derate the operating conditions based on ambient temperature ...

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... VREF 42 VCLAMP 43 OSD31 44 NOTES 1. OSDSxx: OSD SELECT FOR OUTxx OSDxx: OSD VIDEO INPUT FOR OUTxx 2. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND. ADV3200/ADV3201 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Rev Page VNEG 132 131 OSD11 130 OSD12 129 OSD13 ...

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... VPOS Analog Positive Power Supply. 95 IN31 Input Number 31. 96 OSDS31 Control Pin: OSD Select Number 31. 97 IN30 Input Number 30. 98 OSDS30 Control Pin: OSD Select Number 30. 99 IN29 Input Number 29. 100 OSDS29 Control Pin: OSD Select Number 29. Rev Page ADV3200/ADV3201 ...

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... ADV3200/ADV3201 Pin Mnemonic Description 101 IN28 Input Number 28. 102 OSDS28 Control Pin: OSD Select Number 28. 103 IN27 Input Number 27. 104 OSDS27 Control Pin: OSD Select Number 27. 105 IN26 Input Number 26. 106 OSDS26 Control Pin: OSD Select Number 26. 107 IN25 Input Number 25. ...

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... LSB LSB MSB LSB MSB 189 188 187 186 7 CLR Q CLR Q CLR Q CLR Q DECODE 1024 SWITCH MATRIX Figure 6. Logic Diagram Rev Page ADV3200/ADV3201 CLR CLR CLR CLR CLR CLR CLK CLK CLK CLK CLK ...

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... VCLAMP 50µA VNEG Figure 14. VCLAMP Input (See Also Figure 16) VPOS VPOS 2.5kΩ (5kΩ FOR ADV3201) VREF 2.5kΩ (5kΩ FOR ADV3201) VNEG Figure 15. VREF Input (See Also Figure 16) VPOS DVCC OSD, IN, OUT VNEG DGND Figure 16. ESD Protection Map CLK, RESET, UPDATE, CS, ...

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... Figure 20. ADV3200 Large Signal Frequency Response with Capacitive Loads, OSDxx INxx 100 1k 10pF 5pF 2pF 0pF 100 1k Figure 22. ADV3200 OSD Large Signal Frequency Response with Capacitive Rev Page ADV3200/ADV3201 2 1 5pF 10pF 2pF 0 0pF –1 –2 –3 – 100 ...

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... ADV3200/ADV3201 600 500 400 300 200 100 0 354 362 370 378 FREQUENCY (MHz) Figure 23. ADV3200 −3 dB Bandwidth Histogram, One Device, All 1024 Channels 500 475 450 425 400 375 350 325 300 NUMBER OF ENABLED CHANNELS Figure 24. ADV3200 Small Signal Bandwidth vs. Enabled Channels 0 – ...

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... Figure 32. ADV3200 Output Impedance, Disabled 100 Figure 33. ADV3200 Output Impedance, Enabled 0.12 0.08 0.04 0 –0.04 –0.08 –0. Figure 34. ADV3200 Small Signal Pulse Response, 200 mV p-p Rev Page ADV3200/ADV3201 1 10 100 1k FREQUENCY (MHz) 10 100 1k FREQUENCY (MHz) OSDxx INxx TIME (ns) ...

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... ADV3200/ADV3201 1.2 0.8 0.4 0 –0.4 –0.8 –1 TIME (ns) Figure 35. ADV3200 Large Signal Pulse Response p-p 2 UPDATE –1 V – TIME (ns) Figure 36. ADV3200 Switching Time 2 OSDS 1 0 –1 V – TIME (ns) Figure 37. ADV3200 OSD Switching Time INxx OSDxx 14 16 ...

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... Rev Page ADV3200/ADV3201 0 –0.7 –0.5 –0.3 –0.1 0.1 0.3 INPUT DC OFFSET (V) Subcarrier Amplitude = 300 mV p (BROADCAST) POS NEG (ALL OUTPUTS DISABLED) POS NEG –50 –30 –10 ...

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... ADV3200/ADV3201 250 200 150 100 50 0 OFFSET (mV) Figure 47. ADV3200 Input Offset Distribution, One Device, All 1024 Channels 1.5 UPDATE 1.0 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 48. ADV3200 Enable Time )/V OUT OUT – TIME (ns) Figure 49 ...

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... TIME (ns) Figure 54. ADV3200 OSD Large Signal Pulse with Capacitive Loads p –1 – Rev Page ADV3200/ADV3201 V = ±1.45V ±1.65V ±1.65V OUT ±1.45V OUT 100 150 TIME (ns) Figure 55 ...

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... FREQUENCY (MHz) Figure 58. ADV3201 Small Signal Frequency Response with Capacitive Loads, 200 mV p-p INxx OSDxx 100 1k Figure 59. ADV3201 Large Signal Frequency Response with Capacitive Loads, INxx 100 1k 10pF 5pF 2pF 0pF 100 1k Figure 61. ADV3201 OSD Large Signal Frequency Response with Capacitive Rev ...

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... FREQUENCY (MHz) Figure 62. ADV3201 −3 dB Bandwidth Histogram, One Device, All 1024 Channels 350 340 330 320 310 300 NUMBER OF ENABLED CHANNELS Figure 63. ADV3201 Small Signal Bandwidth vs. Enabled Channels 10 0 –10 –20 VPOS –30 VNEG –40 –50 –60 –70 0.1 ...

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... FREQUENCY (MHz) Figure 71. ADV3201 Output Impedance, Disabled 100 100 FREQUENCY (MHz) Figure 72. ADV3201 Output Impedance, Enabled 0.12 0.08 0.04 0 –0.04 –0.08 INxx –0. TIME (ns) Figure 73. ADV3201 Small Signal Pulse Response, 200 mV p OSDxx ...

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... INxx –1 TIME (ns) Figure 74. ADV3201 Large Signal Pulse Response p-p 2 UPDATE V RISING EDGE OUT FALLING EDGE OUT –1 – TIME (ns) Figure 75. ADV3201 Switching Time 2 OSDS V RISING EDGE OUT 1 0 –1 V FALLING EDGE OUT – ...

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... INPUT DC OFFSET (V) Figure 82. ADV3201 OSD Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 0.10 0.05 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 0.3 0.5 0.7 Figure 83. ADV3201 OSD Differential Phase, Carrier Frequency = 3.58 MHz, 300 280 260 240 220 200 180 160 140 120 0.3 0.5 0.7 300 275 250 ...

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... V RISING EDGE OUT –1 V FALLING EDGE OUT –2 80 100 Figure 90. ADV3201 Small Signal Pulse with Capacitive Loads, 200 mV p-p 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1 Figure 91. ADV3201 OSD Small Signal Pulse with Capacitive Loads, Rev Page ADV3200/ADV3201 140 120 ...

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... Figure 92. ADV3201 Large Signal Pulse with Capacitive Loads p-p 1.5 5pF 10pF 1.0 2pF 0pF 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 93. ADV3201 OSD Large Signal Pulse with Capacitive Loads p –1 –2 – Rev Page ±2. ± ...

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... VREF pin. This voltage is common to the entire chip and needs to be driven from a low impedance source to avoid crosstalk. OUT00 Figure 96. Conceptual Diagram of Single Output Channel (ADV3201) Each input to the ADV3200/ADV3201 is buffered by a receiver. This receiver provides overvoltage protection for the input stages by limiting signal swing. In the ADV3200, the output of the receiver is limited to ± ...

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... DVCC/DGND supply pins). However, in order to easily interface to ground referenced video signals, split supply operation is possible with ±2.5 V. (The ADV3201 is intended to operate on ±3.3 V.) In the case of split supplies, a flexible logic interface allows the control logic supplies (DVCC/DGND run off 3.3 V V/0 V while the core remains on split supplies ...

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... The second-rank latches are asynchronous and, when UPDATE is low, they are transparent. If more than one ADV3200/ADV3201 device serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain ...

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... Signals that do not have sync-tips appear distorted if they are run through the clamp function. The range of VCLAMP is − +0.3 V for the ADV3200 at ±2.5 V operation, and −0 +0.3 V for the ADV3201 at ±3.3 V operation. If driving VCLAMP externally, refer to Figure 14 for the input circuitry. Note that the VCLAMP pin has a 6 kΩ ...

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... MAX MAX For example, if the ADV3200/ADV3201 is enclosed in an environ- ment at 45° the total on-chip dissipation under all load A and supply conditions must not be allowed to exceed 6.5 W. When calculating on-chip power dissipation necessary to include the rms current being delivered to the load, multiplied by the rms voltage drop on the ADV3200/ADV3201 output devices ...

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... When there are many signals in close proximity in a system undoubtedly the case in a system that uses the ADV3200/ ADV3201, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of OUTPUT terms is required in order to specify a system that uses one or more crosspoint devices ...

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... As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 32 × 32 matrix of the ADV3200/ADV3201, note the number of crosstalk terms that can be considered for a single channel, for example, the IN00 input. IN00 is programmed to connect to one of the ADV3200/ ADV3201 outputs where the measurement can be made ...

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... As frequencies of operation increase, proper routing of trans- mission line signals becomes more important. The bandwidth (5) of the ADV3200/ADV3201 is large enough so that using high impedance routing does not provide a flat in-band frequency response for practical signal trace lengths necessary for the user to choose a characteristic impedance suitable for the application and to properly terminate the input and output signals of the ADV3200/ADV3201 ...

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... For this reason, place back-termination resistors close to the ADV3200/ADV3201. In practice, because back-termination resistors are series elements, their footprint in the routing is narrower, and it is easier to place them close to the ADV3200/ ADV3201 outputs in board layout. VPOS VNEG DVCC DGND OUT[31], OUT[15:0] OUT[18:16] ...

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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADV3200ASWZ −40°C to +85°C ADV3201ASWZ 1 −40°C to +85° RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07176-0-10/08(0) 26 ...