ADV3201 AD [Analog Devices], ADV3201 Datasheet - Page 11

• Manufacturer Part Number: ADV3201
• Manufacturer: AD [Analog Devices]

TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table
CS
X
0
0
1
1
2
UPDATE
X = don’t care.
Data
1
CLK
CS
i
: serial data.
RESET
RESET
DATA
UPDATE
X
1
0
X
IN
D
CLR
CLR Q
LE
CLK
OUT00
LSB
192
0
Q
D
CLK
X
X
X
D
CLR
LE
CLR Q
CLK
OUT00
LSB
191
1
Q
D
D
CLR
CLR Q
CLK
LE
OUT00
DATA IN
X
Data
X
X
LSB
190
2
Q
D
i
2
D
CLR
CLR Q
CLK
LE
OUT00
LSB
189
3
Q
D
D
CLR
CLR Q
LE
CLK
OUT00
DATA OUT
X
Data
X
X
LSB
188
4
Q
D
i-193
D
CLR
CLR Q
LE
CLK
OUT00
MSB
187
EN
Q
D
Figure 6. Logic Diagram
D
CLR
CLR Q
LE
CLK
OUT01
RESET
0
1
1
1
Rev. 0 | Page 11 of 36
LSB
186
0
Q
SWITCH MATRIX
D
DECODE
. . .
. . .
1024
D
CLR
CLR Q
CLK
LE
OUT30
Operation/Comment
Asynchronous reset. All outputs are disabled. The 193-bit shift
register is reset to all 0s.
The data on the serial DATA IN line is loaded into the serial
register. The first bit clocked into the serial register appears at
DATA OUT 193 clock cycles later.
Switch matrix update. Data in the 193-bit shift register is trans-
ferred into the parallel latches that control the switch array and
sync-tip clamps.
Chip is not selected. No change in logic.
MSB
EN
7
Q
D
D
CLR
LE
CLR Q
CLK
OUT31
LSB
0
6
Q
D
D
CLR
CLR Q
CLK
LE
OUT31
LSB
1
5
Q
D
D
CLR
CLR Q
CLK
LE
OUT31
LSB
2
4
Q
D
CLR
D
CLR Q
CLK
LE
OUT31
LSB
3
3
Q
D
D
CLR
ADV3200/ADV3201
CLR Q
CLK
LE
OUT31
LSB
4
2
Q
D
D
CLR
CLR Q
CLK
LE
OUT31
MSB
EN
1
Q
D
D
CLR
CLR Q
CLK
LE
OUT31
SYNC
TIP
EN
0
Q
D
OUTPUT
ENABLE
DATA
OUT
32