CS8401A-IP ETC [List of Unclassifed Manufacturers], CS8401A-IP Datasheet - Page 17

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CS8401A-IP

Manufacturer Part Number
CS8401A-IP
Description
Digital Audio Interface Transmitter
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
RD/WR - Read/Write, PIN 16.
A4-A0 - Address Bus, PINS 9-13.
D0-D7 - Data Bus, PINS 21-24, 1-4.
INT - Interrupt, PIN 15.
Transmitter Interface
MCK - Master Clock, PIN 5.
TXP, TXN - Differential Line Drivers, PINS 20, 17.
DS60F1
If RD/WR is low when CS goes active (low), the data on the data bus is written to internal
memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on
the data bus.
Parallel port address bus that selects the internal memory location to be read from or written to.
Parallel port data bus used to check status, write control words, or write internal buffer memory.
Open drain output that can signal the state of the internal buffer memory. A 5k
VD+ is typically used to support logic gates. All bits affecting INT are maskable allowing total
control over the interrupt mechanism.
Clock input which defines the transmit timing. It can be configured, via control register 2, for
128, 192, 256, or 384 times the sample rate.
RS422 compatible line drivers. Drivers are pulled low when part is in reset state.
CS8401A
resistor to
17

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