CS8401A-IP ETC [List of Unclassifed Manufacturers], CS8401A-IP Datasheet - Page 9

• Manufacturer Part Number: CS8401A-IP
• Description: Digital Audio Interface Transmitter
• Manufacturer: ETC [List of Unclassifed Manufacturers]

digital audio specifications, V = 0 signifies the
audio signal is suitable for conversion to analog.
B1 and B0 select one of three modes for the
buffer memory. The different modes are shown
in Figure 5 and the bit combinations in Table 2.
More information on the different modes can be
found in the Buffer Memory section. Bit 2, CRCE, is
the channel status CRCC enable and should only be
used in professional mode. When CRCE is high, the
A
D
D
R
E
S
S
DS60F1
1A
1B
1C
1D
1E
1F
10
11
12
13
14
15
16
17
18
19
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
Figure 5. CS8401A Buffer Memory Modes
C. S. Data
20 Bytes
Channel
1st Four
Bytes of
Status
Data
Last
0
Status register 0
Control Register 1
Control Register 2
Control Register 3
C. S. Data
User Data
Auxiliary
1st Four
Bytes of
C. S.
Data
Data
Memory Mode
1
C. S. Data
Left C. S.
1st Four
1st Four
Bytes of
Bytes of
Right
Right
C. S.
C. S.
Data
Data
Data
Left
2
U
N
D
E
F
I
N
E
D
3
X:00
FLAG2: High for first four bytes of channel status
FLAG1: Memory mode dependent - See figure 11
FLAG0: High for last two bytes of user data.
X:01
BKST: Causes realignment of data block when set to "1".
TRNPT: Selects Transparent Mode appropriately setting data
MASK2: Interrupt mask for FLAG2. A "1" enables the interrupt.
MASK1: Interrupt mask for FLAG1.
MASK0: Interrupt mask for FLAG0.
X:02
M1: with M0, selects MCK frequency.
M0: with M1, selects MCK frequency.
V: Validity bit of current sample.
B1: with B0, selects the buffer memory mode.
B0: with B1, selects the buffer memory mode.
CRCE: Channel status CRC Enable. Professional mode only.
MUTE: When clear, transmitted audio data is set to zero.
RST: When clear, drivers are disabled, frame counters cleared.
B1
0
0
1
1
M1
0
0
1
1
BKST
delay through device
M1
7
7
7
B0
0
1
0
1
Table 2. Buffer Memory Modes
TRNPT
M0
Table 1. MCLK Frequencies
Figure 7. Control Register 1
Figure 8. Control Register 2
6
6
6
Figure 6. Status Register
M0
0
1
0
1
Mode
V
0
1
2
3
5
5
5
B1
Independent Channel Status
4
4
4
Buffer Memory Contents
128 Input Word Rate
192 Input Word Rate
256 Input Word Rate
384 Input Word Rate
B0
Channel Status
3
3
3
Auxiliary Data
Reserved
MCLK
MASK2
CRCE
FLAG2
2
2
2
CS8401A
MASK1
FLAG1
MUTE
1
1
1
MASK0
FLAG0
RST
0
0
0
9