LMH7322_0706 NSC [National Semiconductor], LMH7322_0706 Datasheet - Page 15

• Manufacturer Part Number: LMH7322_0706
• Description: Dual 700 ps High Speed Comparator with RSPECL Outputs
• Manufacturer: NSC [National Semiconductor]

TIPS & TRICKS USING THE LMH7322
In this section several aspects are discussed concerning spe-
cial applications using the LMH7322.
This concerns the LE function, the connection of the DAP in
conjunction to the V
terface between several logic families.
THE LATCH ENABLE PINS
The latch function is intended to stop the device from com-
paring the signals on both input pins. If the latch function is
enabled the output is frozen and the logic information on the
output pins, present at that moment is held until the latch
function is disabled. The timing of this process can be seen
in Figure 4. The input levels for the latch pins should comply
with RSPECL, but can also be driven with PECL type of sig-
nals if the minimum supply (V
3.3V. The minimum differential latch input voltage should be
100 mV. Another possibility to set the LE function in a steady
state is to connect the pins via a resistor to the power supply.
If the LE pin is connected to V
the LE-not pin is connected via 10 kΩ to the V
is continuously on. Since the latch input stage is referenced
to V
nected to this voltage. This is very important when working
with different voltages for V
wrong supply the latch function will not work.
THE DAP AND THE VEE PINS
To assure that both VEE pins are always operating at the
same voltage level both VEE pins are connected to the DAP.
This means the DAP is always at the lowest power supply
level. This gives also the possibility to power the part via the
DAP which means there are bond wires used for the connec-
tion to the VEE pins. A beter solution is to external connect
the VEE and the DAP by pcb track. (see Figure 5).
To protect the device during handling and production two anti-
parallel connected diodes are connected between both VEE
Interface from PECL to (RS)ECL
The conversion from PECL to RS-ECL is possible when con-
necting the V
handle these positive levels. The V
CCO
, the resistors to set the LE function should be con-
CCI
pin to +5V, which allows the input stage to
EE
pins and the use of this part as an in-
CCI
CCO
EE
and V
via a resistor of 10 kΩ and
–V
CCO
CCO
EE
pin must be connected
) is larger or equal to
. If connected to the
CCO
pin the part
FIGURE 6. ECL TO RSPECL
15
pins. Under normal operating conditions these diodes are
shortened via the DAP.
The DAP (Die Attach Paddle) functions as a heat sink which
means that heat can be transferred using vias below this pad
to any appropriate copper plane.
INTERFACE BETWEEN LOGIC FAMILIES
As can be seen in the typical schematics (see the first part of
the datasheet) the LMH7322 can be used to interface be-
tween different logic families. The feature that facilitates this
property is the fact that the input stage and the output stage
use different positive power supply pins which can be used at
different supply voltages. The negative supply pins are con-
nected together for both parts. Using the power pins at differ-
ent supply voltages makes it possible to create several
translations for logic families. It is possible to translate from
logic at negative voltage levels such as ECL to logic at positive
levels such as RSPECL and LVDS and vice versa.
Interface from ECL to RSPECL
The supply pin V
input levels are negative and the V
to create the RSPECL levels (see Figure 6). When working
with ECL, the negative supply pin (V
the −5.2V ECL supply voltage.
to the ground level in order to create the RSECL levels. The
high level of the output of the LMH7322 is normally 1.1V below
the V
supply. The output levels are now −1100 mV for the logic ‘1’
CCO
supply voltage, and the low level is 1.5V below this
FIGURE 5. DAP Connection
CCI
can be connected to ground because the
CCO
EE
pin must operate at 5V
) can be connected to
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