X98017L128-3.3 INTERSIL [Intersil Corporation], X98017L128-3.3 Datasheet - Page 6

• Manufacturer Part Number: X98017L128-3.3
• Description: 170MHz Triple Video Digitizer with Digital PLL
• Manufacturer: INTERSIL [Intersil Corporation]

R
R
P
S
/G
/G
DATACLK
DATACLK
HSYNC
HSYNC
Video In
P
S
Video In
G
R
B
/B
/B
Analog
Analog
P
P
P
HS
HS
[7:0]
[7:0]
[7:0]
P
S
[7:0]
[7:0]
OUT
OUT
IN
IN
P
P
0
0
6
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
P
P
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
1
1
t
HSYNCin-to-HSout
t
HSYNCin-to-HSout
P
P
2
2
8.5 DATACLK Pipeline Latency
8.5 DATACLK Pipeline Latency
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
FIGURE 3. 24 BIT OUTPUT MODE
P
P
= 7.5ns + (PHASE/64 +8.5)*t
3
3
= 7.5ns + (PHASE/64 +8.5)*t
P
P
X98017
4
4
Width and Polarity
Width and Polarity
P
P
Programmable
Programmable
5
5
PIXEL
P
P
PIXEL
6
6
P
P
7
7
P
P
8
8
G
B
0
0
D
(U
(Y
0
o
o
P
P
)
)
9
9
G
R
1
1
D
(V
(Y
1
P
P
1
1
10
)
)
10
G
B
2
2
D
(U
(Y
2
P
P
2
2
11
)
)
11
D
June 6, 2005
3
P
P
FN8218.0
12
12