X98017L128-3.3 INTERSIL [Intersil Corporation], X98017L128-3.3 Datasheet - Page 7

• Manufacturer Part Number: X98017L128-3.3
• Description: 170MHz Triple Video Digitizer with Digital PLL
• Manufacturer: INTERSIL [Intersil Corporation]

R
R
R
R
P
S
P
S
/G
/G
/G
/G
DATACLK
DATACLK
HSYNC
HSYNC
HSYNC
P
S
Video In
P
S
Video In
/B
/B
/B
/B
Analog
Analog
HS
HS
P
S
P
S
[7:0]
[7:0]
[7:0]
[7:0]
OUT
OUT
IN
IN
P
0
P
1
7
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
P
P
0
2
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
t
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
HSYNCin-to-HSout
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
P
P
1
3
t
HSYNCin-to-HSout
FIGURE 5. 48 BIT OUTPUT MODE
= 7.5ns + (PHASE/64 +10.5)*t
P
P
2
4
= 7.5ns + (PHASE/64 +8.5)*t
P
P
3
5
X98017
P
P
4
6
Width and Polarity
PIXEL
P
Width and Polarity
Programmable
P
5
Programmable
7
PIXEL
P
6
P
8
P
7
P
9
P
P
8
10
P
P
9
D
11
0
D
D
0
1
P
10
P
D
12
1
D
2
D
D
P
2
3
11
June 6, 2005
FN8218.0