V62C1801024L-100B MOSEL [Mosel Vitelic, Corp], V62C1801024L-100B Datasheet
V62C1801024L-100B
Related parts for V62C1801024L-100B
V62C1801024L-100B Summary of contents
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... REV. 1.1 April 2001 V62C1801024L(L) Functional Description The V62C1801024L is a low power CMOS Static RAM or- ganized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE , and Tri-state I/O’s. This device has an a- utomatic power-down mode feature when deselected. ...
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... A Top View 48-CSP Ball-Grid Array package (shading indicates no ball REV. 1.1 April 2001 V62C1801024L( TOP VIEW CE2 ...
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... Key Don’t Care Low High Recommended Operating Conditions Parameter Supply Voltage Input Voltage * V min = -1.0V for pulse width less than For Industrial Temperature. REV. 1.1 April 2001 V62C1801024L(L) Symbol Minimum Tstg Tbias WE OE Data X X High High-Z ...
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... This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 70ns/85 ns Load 100ns/150 ns REV. 1.1 April 2001 V62C1801024L( 1.8 to 2.2V, Gnd = 0V Test Conditions Sym Min Max Min Max Min Max Min Max I V ...
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... Address Setup Time Write Pulse Width Write Recovering Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End REV. 1.1 April 2001 V62C1801024L(L) = 1.8 to 2.2V, Gnd = 0V Symbol -70 Min Max Min Max Min Max Min Max ...
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... Timing Waveform of Read Cycle 1 Address D OUT Timing Waveform of Read Cycle 2 CE1 OE D OUT Supply Current Timing Waveform of Read Cycle 3 CE2 OE D OUT Supply Current REV. 1.1 April 2001 V62C1801024L(L) (3,6,7,9) (Address Controlled Data Valid (5,6,8,9) (CE1 Controlled OLZ t ACE ...
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... Timing Waveform of Write Cycle 1 Address OUT Timing Waveform of Write Cycle 2 Address CE1 OUT Timing Waveform of Write Cycle 3 Address CE2 OUT REV. 1.1 April 2001 V62C1801024L(L) (10,11) (WE Controlled Data Valid t WZ (10,11) (CE1 Controlled ...
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... All read cycle timings are referenced from the last valid address to the first transtion address. 10. CE1 or WE must be HIGH or CE2 must be LOW during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.1 April 2001 V62C1801024L(L) (L Version Only) Symbol ...
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... V62C1801024LL-85V V62C1801024LL-100V V62C1801024LL-150V V62C1801024L(L)-70B V62C1801024L(L)-85B V62C1801024L(L)-10 0B V62C1801024L(L)-150 B * For Indu strial Temperature tested devices, an “I” designator will be added to the end of the device number. REV. 1.1 April 2001 V62C1801024L(L) V62C1801024L(L) Speed Package 32-pin Plastic TSOP1 85 ns 100 ns ...
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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V62C1801024L(L) UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE ...