V62C1801024L-100B MOSEL [Mosel Vitelic, Corp], V62C1801024L-100B Datasheet - Page 8

• Manufacturer Part Number: V62C1801024L-100B
• Description: Ultra Low Power 128K x 8 CMOS SRAM
• Manufacturer: MOSEL [Mosel Vitelic, Corp]

REV. 1.1 April 2001 V62C1801024L(L)
Data Retention Characteristics
Data Retention Waveform
Notes
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
1. L-version includes this feature.
2. This Parameter is sampled and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
CC
for Data Retention
V
CE
CC
Parameter
(2)
Vcc_typ
(L Version Only) (T
t
CDR
V
IH
(L Version Only)
Symbol
V
I
t
t
CCDR
R
CDR
DR
Data Retention Mode
V
DR
8
V
> 1.0V
DR
A
V
CE
CE
V
Test Condition
= 0
IN
IN
(1)
1
2
> V
< 0.2V
> V
< + 0.2V
0
C to +70
CC
CC
- 0.2V or
- 0.2V or
V
V62C1801024L(L)
t
0
Vcc_typ
R
IH
C / -40
0
C to +85
Min
t
1.0
RC
0
-
0
C)
Max
1
-
-
-
Unit
ns
ns
V
A