AT25128A-W1.8-11 ATMEL [ATMEL Corporation], AT25128A-W1.8-11 Datasheet - Page 7

• Manufacturer Part Number: AT25128A-W1.8-11
• Description: SPI Serial EEPROMs
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
3368H–SEEPR–8/05
The AT25128A/256A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in see Table 5. All instructions, addresses, and data
are transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25128A/256A
WRITE ENABLE (WREN): The device will power-up in the write disable state when V
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Table 7. Read Status Register Bit Definition
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4 − 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0 − 7 are “1”s during an internal write cycle.
WPEN
Bit 7
Bit 6
X
Definition
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
See Table 8 on page 8.
See Table 8 on page 8.
See Table 9 on page 8.
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Bit 5
X
Bit 4
X
Bit 3
BP1
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
AT25128A/256A
Bit 2
BP0
WEN
Bit 1
Bit 0
RDY
CC
7