AT25128A-W1.8-11 ATMEL [ATMEL Corporation], AT25128A-W1.8-11 Datasheet - Page 8

• Manufacturer Part Number: AT25128A-W1.8-11
• Description: SPI Serial EEPROMs
• Manufacturer: ATMEL [ATMEL Corporation]

8
AT25128A/256A
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128A/256A is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of
the data within any selected segment will therefore be read only. The block write protec-
tion levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, t
Table 8. Block Write Protect Bits
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 9. WPEN Operation
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the Read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10 on
page 9). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read,
the CS line should be driven high after the data comes out. The read sequence can be
continued since the byte address is automatically incremented and data will continue to
be shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous read cycle.
WPEN
Level
1(1/4)
2(1/2)
3(All)
0
0
0
1
1
X
X
High
High
Low
Low
WP
X
X
BP1
Status Register Bits
0
0
1
1
WEN
0
1
0
1
0
1
BP0
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
AT25128A
Array Addresses Protected
None
Unprotected
WC
Protected
Protected
Protected
Writable
Writable
Writable
Blocks
, RDSR).
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
AT25256A
3368H–SEEPR–8/05
None
Protected
Protected
Protected
Protected
Register
Writable
Writable
Status