AT25320B ATMEL [ATMEL Corporation], AT25320B Datasheet - Page 6

• Manufacturer Part Number: AT25320B
• Description: SPI Serial EEPROMs 32K (4096 x 8) 64K (8192 x 8)
• Manufacturer: ATMEL [ATMEL Corporation]

Table 0-4.
Applicable over recommended operating range from T
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Note:
1. Serial Interface Description
6
Symbol
t
t
t
t
Endurance
LZ
HZ
DIS
WC
1. This parameter is characterized and is not 100% tested.
AT25320B/640B
(1)
AC Characteristics (Continued)
Parameter
HOLD to Output Low Z
HOLD to Output High Z
Output Disable Time
Write Cycle Time
3.3V, 25°C, Page Mode
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25320B/640B always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25320B/640B has separate pins designated for data trans-
mission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25320B/640B, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25320B/640B is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25320B/640B.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
AI
=
–
40°C to +85°C, V
Voltage
4.5–5.5
2.7–5.5
1.8–5.5
4.5–5.5
2.7–5.5
1.8–5.5
4.5–5.5
2.7–5.5
1.8–5.5
4.5–5.5
2.7–5.5
1.8–5.5
CC
= As Specified,
Min
1M
0
0
0
Max
100
200
200
25
50
40
80
40
80
5
5
5
8535B–SEEPR–7/08
Write Cycles
Units
ms
ns
ns
ns