IS42S16100-10TI ISSI [Integrated Silicon Solution, Inc], IS42S16100-10TI Datasheet - Page 31
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IS42S16100-10TI
Manufacturer Part Number
IS42S16100-10TI
Description
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ISSI [Integrated Silicon Solution, Inc]
Datasheet
1.IS42S16100-10TI.pdf
(78 pages)
- Current page: 31 of 78
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IS42S16100
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
11/01/01
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
WDL
) from the precharge command to the point
CLK
I/O
DQM
CLK
I/O
WRITE (CA=A, BANK 0)
WRITE A0
D
IN
WRITE (CA=A, BANK 0)
A0
D
WRITE A0
IN
D
IN
A0
A1
D
IN
D
IN
A1
A2
D
1-800-379-4774
IN
D
IN
A2
t
A3
DPL
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
PRECHARGE (BANK 0)
D
PRE 0
CAS
CAS
CAS
CAS
CAS Latency
PRE 0
IN
A3
MASKED BY DQM
t
t
WDL
PRECHARGE (BANK 0)
DPL
t
WDL
=0
DPL
) has elapsed. Therefore, the
3
0
1
ISSI
2
0
1
31
®
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