M95320-W STMICROELECTRONICS [STMicroelectronics], M95320-W Datasheet - Page 17

• Manufacturer Part Number: M95320-W
• Description: 32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95320, M95640, M95320-x, M95640-x
6.3
6.3.1
6.3.2
6.3.3
6.3.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in
The Status Register format is shown in
Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register Write Protect
SRWD
b7
Status Register format
0
0
Table 4
0
Table
and the status and control bits of the Status
4) becomes protected against Write
BP1
Block Protect Bits
Figure
Write Enable Latch Bit
9.
BP0
Write In Progress Bit
WEL
Instructions
WIP
b0
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