M95320-DRMN6TP STMicroelectronics, M95320-DRMN6TP Datasheet
M95320-DRMN6TP
Specifications of M95320-DRMN6TP
Related parts for M95320-DRMN6TP
M95320-DRMN6TP Summary of contents
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... Write Protect: quarter, half or whole memory array ■ High-speed clock: 20 MHz ■ Single supply voltage: – 2 5.5 V for M95320-W – 1 5.5 V for M95320-R – 1 5.5 V for M95320-DF ■ Operating temperature range: from -40° +85°C ■ Enhanced ESD protection ■ ...
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... Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF ...
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... Write to Memory Array (WRITE 6.6.1 6.7 Read Identification Page (available only in M95320-D devices 6.8 Write Identification Page (available only in M95320-D devices 6.9 Read Lock Status (available only in M95320-D devices 6.10 Lock ID (available only in M95320-D devices Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. DC characteristics (M95320-W, device grade Table 17. DC characteristics (M95320-R, device grade Table 18. DC characteristics (M95320-DF, device grade 6 Table 19. AC characteristics (M95320-W, device grade Table 20. AC characteristics (M95320-R, M95320-DF, device grade Table 21. SO8N – ...
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... M95320-W M95320-R M95320-DF List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections (top view Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 ...
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... The M95320 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 4096 x 8 bits, accessed through the SPI bus. The M95320 devices can operate with a supply range from 1 5.5 V, and are guaranteed over the -40 °C/+85 °C temperature range. The M95320-D offers an additional page, named the Identification Page (32 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode ...
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... M95320-W M95320-R M95320-DF Figure 2. 8-pin package connections (top view) 1. See Section 10: Package mechanical data M95xxx HOLD AI01790D section for package dimensions, and how to identify pin 1. Doc ID 5711 Rev 15 Description 7/46 ...
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... Memory organization 2 Memory organization The memory is organized as shown in the following figure. Figure 3. Block diagram 8/46 M95320-W M95320-R M95320-DF Doc ID 5711 Rev 15 ...
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... M95320-W M95320-R M95320-DF 3 Signal description During all operations (min (max All of the input and output signals must be held high or low (according to voltages specified described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C) ...
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... Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 V supply voltage the supply voltage. CC 3.8 V ground the reference for all signals, including the V SS 10/46 M95320-W M95320-R M95320-DF supply voltage. CC Doc ID 5711 Rev 15 ...
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... M95320-W M95320-R M95320-DF 4 Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. ...
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... Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 5. SPI modes supported CPOL CPHA 12/46 MSB Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF Figure 5, is the clock polarity when the MSB AI01438B ...
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... M95320-W M95320-R M95320-DF 5 Operating features 5.1 Supply voltage (V 5.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V in Section 9: DC and AC end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t ...
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... In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. 14/ (a)(b) Hold condition Figure 6). Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF supply voltage below the minimum CC Section 9: DC and AC Section 9: DC and AC parameters). Hold condition ), CC ai02029E ...
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... M95320-W M95320-R M95320-DF The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions ...
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... Write to Memory Array Reads the page dedicated to identification. Writes the page dedicated to identification. Reads the lock status of the Identification Page. Locks the Identification page in read-only mode. Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF Table 4. Table 4), the device automatically Instruction format 0000 0110 ...
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... M95320-W M95320-R M95320-DF 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...
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... WRDI instruction execution ● WRSR instruction completion ● WRITE instruction completion. Figure 8. Write Disable (WRDI) sequence 18/ send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 5711 Rev 15 M95320-W M95320-R M95320- AI03750D ...
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... M95320-W M95320-R M95320-DF 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Figure 10 Instruction 7 High Impedance MSB Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Status Register AI02282D b0 WIP ...
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... M95320-W M95320-R M95320-DF Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self- timed Write cycle that takes t and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle t , and 0 when the Write cycle is complete ...
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... Address MSB Table 5, the most significant address bits are Don’t Care. Doc ID 5711 Rev 15 M95320-W M95320-R M95320- Data Out 1 Data Out MSB ...
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... M95320-W M95320-R M95320-DF When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle ...
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... Data Byte Table 5, the most significant address bits are Don’t Care. Doc ID 5711 Rev 15 M95320-W M95320-R M95320- Data Byte Data Byte ...
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... M95320-W M95320-R M95320-DF 6.6.1 Cycling with Error Correction Code (ECC) M95320-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value ...
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... Instructions 6.7 Read Identification Page (available only in M95320-D devices) The Identification Page (32 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D) ...
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... M95320-W M95320-R M95320-DF 6.8 Write Identification Page (available only in M95320-D devices) The Identification Page (32 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D) ...
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... Instructions 6.9 Read Lock Status (available only in M95320-D devices) The Read Lock Status instruction (see Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D) ...
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... M95320-W M95320-R M95320-DF 6.10 Lock ID (available only in M95320-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high ...
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... The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). 30/46 M95320-W M95320-R M95320-DF Doc ID 5711 Rev 15 ...
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... M95320-W M95320-R M95320-DF 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... CC T Ambient operating temperature A Table 10. Operating conditions (M95320-R, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 11. Operating conditions (M95320-DF, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 12. AC measurement conditions Symbol C Load capacitance L Input rise and fall times ...
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... M95320-W M95320-R M95320-DF Table 13. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested Table 14. Cycling performance by groups of four bytes Symbol Parameter Ncycle Write cycle endurance 1. Cycling performance for products identified by process letter K. ...
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... DC and AC parameters Table 16. DC characteristics (M95320-W, device grade 6) Symbol Parameter Input leakage I LI current Output leakage I LO current Supply current I CC (Read) Supply current (2) I CC0 (Write) Supply current I CC1 (Standby) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... Internal reset (3) V RES threshold voltage 1. If the application uses the M95320-R device with 2.5 V < characteristics (M95320-W, device grade 2. For the device identified by process letter K. 3. Characterized only, not tested in production. 4. 0.7 V with the device identified by process letter K. 5. 1.3 V with the device identified by process letter K. ...
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... Input high voltage IH V Output low voltage OL V Output high voltage OH Internal reset (2) V RES threshold voltage 1. If the application uses the M95320-DF devices at 2 characteristics (M95320-W, device grade 2. Characterized only, not tested in production. 36/46 (1) Test conditions ...
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... M95320-W M95320-R M95320-DF Table 19. AC characteristics (M95320-W, device grade 6) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH ...
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... HOLD low to output high-Z HLQZ Write time the application uses the M95320-R or M95320-DF at 2.5 V please refer t to Table 19: AC characteristics (M95320-W, device grade must never be lower than the shortest possible clock period, 1 Characterized only, not tested in production. ...
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... M95320-W M95320-R M95320-DF Figure 19. Serial input timing S tCHSL C tDVCH D Q Figure 20. Hold timing HOLD tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 5711 Rev 15 DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c ...
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... DC and AC parameters Figure 21. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN 40/46 M95320-W M95320-R M95320-DF tCH tCHCL tCL tQLQH tQHQL Doc ID 5711 Rev 15 tSHSL tSHQZ AI01449f ...
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... M95320-W M95320-R M95320-DF 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline A2 1 ...
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... Doc ID 5711 Rev 15 M95320-W M95320-R M95320- TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 ...
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... M95320-W M95320-R M95320-DF Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline 1. Drawing is not to scale. 2. The central pad (area the above illustration) is internally pulled to V connected to any other voltage or signal line on the PCB, for example during the soldering process. ...
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... RoHS compliant and halogen-free (ECOPACK®) (1) Process /P or /K= Manufacturing technology code 1. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. 44/46 M95320-W M95320-R M95320-DF M95320 Doc ID 5711 Rev ...
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... Figure 27: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline. Datasheet split into: – M95320-W, M95320-R, M95320-DR (this datasheet) for standard 14 products (range 6), – M95320-125 datasheet for automotive products (range 3). Removed: – M95320-DR product – MLP rev B package 15 Added: – M95320-DF product Updated: – ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 46/46 Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 5711 Rev 15 M95320-W M95320-R M95320-DF ...