M95320-DRMN6TP STMicroelectronics, M95320-DRMN6TP Datasheet - Page 23

• Manufacturer Part Number: M95320-DRMN6TP
• Description: EEPROM 32Kb SPI bus EEPROM 20 MHz 4kB
• Manufacturer: STMicroelectronics

Specifications of M95320-DRMN6TP

• Rohs: yes

M95320-W M95320-R M95320-DF
6.6
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
S
C
D
Q
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period t
end of which the Write in Progress (WIP) bit is reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
W
0
(as specified in AC characteristics in
1
Figure
High Impedance
Figure
2
Instruction
3
12, to send this instruction to the device, Chip Select (S) is first driven
4
12, Chip Select (S) is driven high after the eighth bit of the data byte
5
Table
6
7
Doc ID 5711 Rev 15
15
5, the most significant address bits are Don’t Care.
8
14 13
9 10
16-Bit Address
3
20 21 22 23 24 25 26 27
2
Section 9: DC and AC
1
0
7
6
5
Data Byte
4
3
28 29 30
Figure
parameters), at the
2
1
13, the next byte
0
31
Instructions
AI01795D
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