M24256-BF STMICROELECTRONICS [STMicroelectronics], M24256-BF Datasheet - Page 6

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M24256-BF

Manufacturer Part Number
M24256-BF
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Description
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Description
The M24256-Bx devices are I
(EEPROM). They are organized as 32 Kb × 8 bits.
The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance
with the I
when accessing the identification page.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Table 1.
E0, E1, E2
SDA
SCL
WC
V
V
CC
SS
2
Signal name
C bus definition. The M24256-DR also decodes the type identifier code (1011)
Logic diagram
Signal names
Table
2
Doc ID 6757 Rev 21
C-compatible electrically erasable programmable memories
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
2), terminated by an acknowledge bit.
2
M24256-BF, M24256-BR, M24256-BW, M24256-DR
C protocol, with all memory operations synchronized
Function
Inputs
I/O
Input
Input
Direction
th
bit

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