M45PE40-VMP6 STMICROELECTRONICS [STMicroelectronics], M45PE40-VMP6 Datasheet
M45PE40-VMP6
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M45PE40-VMP6 Summary of contents
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... Deep Power-down Mode 1 A (typical) Electronic Signature – JEDEC Standard Two-Byte Signature (4013h) More than 100000 Write Cycles More than 20 Year Data Retention Packages – ECOPACK® (RoHS compliant) October 2005 Figure 1. Packages VDFPN8 (MP) 6x5mm (MLP8 SO8W (MW) 208 mils width M45PE40 1/35 ...
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... M45PE40 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Reset (Reset Write Protect ( SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Polling During a Write, Program or Erase Cycle ...
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... INITIAL DELIVERY STATE MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REVISION HISTORY M45PE40 3/35 ...
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... M45PE40 SUMMARY DESCRIPTION The M45PE40 is a 4Mbit (512K x 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle fol- lowed by a Page Program cycle ...
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... Hardware Protected mode, when Write Protect (W) is connected to V 256 pages of memory to become read-only by pro- tecting them from write, program and erase oper- ations. When Write Protect (W) is connected the first 256 pages of memory behave like CC the other pages of memory. M45PE40 , causing the first SS 5/35 ...
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... M45PE40 SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 4 ...
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... Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops CC1 The Deep Power-down mode is entered when the specific instruction (the Deep Power-down (DP) in- struction) is executed. The device consumption drops further to I CC2 M45PE40 and AC Characteristics , The Write ...
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... The environments where non-volatile memory de- vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE40 features the following data protection mechanisms: Power On Reset and an internal timer (t can provide protection against inadvertant changes while the power supply is outside the operating specification ...
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... The device is Page or Sector Erasable (bits are erased from 0 to 1). Table 3. Memory Organization Sector Address Range 7 70000h 6 60000h 5 50000h 4 40000h 3 30000h 2 20000h 1 10000h 0 00000h M45PE40 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh 9/35 ...
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... M45PE40 Figure 6. Block Diagram Reset W Control Logic Address Register and Counter 10/35 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 10000h 00000h 256 Bytes (Page Size) X Decoder Status Register 7FFFFh First 256 Pages can be made read-only 000FFh AI04042B ...
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... Erase cycle continues unaffected. One-byte Instruction Code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0011 0000 1011 0000 1010 0000 0010 1101 1011 1101 1000 1011 1001 1010 1011 M45PE40 Address Dummy Bytes Bytes 06h 0 0 04h 0 0 9Fh 0 0 ...
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... M45PE40 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set pri every Page Write (PW), Page Program (PP), Figure 7. Write Enable (WREN) Instruction Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit ...
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... Standby Power mode, the device waits to be se- lected, so that it can receive, decode and execute instructions. Device Identification Memory Type 40h Manufacturer Identification MSB Memory Capacity 13h Device Identification MSB AI06809b M45PE40 Figure 9.. 13/35 ...
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... M45PE40 Read Status Register (RDSR) The Read Status Register (RDSR) instruction al- lows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When one of these cycles is in progress rec- ommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Erase, Program or Write cycle is in Figure 11.. progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB Data Out 1 Data Out MSB AI03748D M45PE40 15/35 ...
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... M45PE40 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C) ...
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... Address MSB Data Byte MSB operation)). Data Byte MSB Data Byte MSB AI04045 M45PE40 17/35 ...
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... M45PE40 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write En- able (WREN) instruction must previously have been executed. After the Write Enable (WREN) in- struction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is rejected Figure 15.. without having any effects on the cycle that is in progress Instruction 24 Bit Address 23 22 MSB M45PE40 ) is initiated. While the Page Erase cy AI04046 19/35 ...
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... M45PE40 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decod- ed, the device sets the Write Enable Latch (WEL). ...
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... Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is re- jected without having any effects on the cycle that is in progress Instruction Stand-by Mode CC2 DP Deep Power-down Mode M45PE40 Figure 17.. before the DP and the Deep AI03753D 21/35 ...
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... M45PE40 Release from Deep Power-down (RDP) Once the device has entered the Deep Power- down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruc- tion. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) in- ...
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... Table 6.. tVSL Read Access allowed tPUW , has elapsed, after V VSL CC (min), the device can be selected for CC delay is not yet PUW supply. Each de drops from the operat all operations are disabled WI Device fully accessible time M45PE40 has risen rail decou- AI04009C 23/35 ...
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... M45PE40 Table 6. Power-Up Timing and V Symbol 1 V (min low t CC VSL 1 Time delay before the first Write, Program or Erase instruction t PUW 1 Write Inhibit Voltage V WI Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C. INITIAL DELIVERY STATE ...
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... Input Levels Timing Reference Levels 0.8V CC 0.2V CC Test Condition OUT =25°C and a frequency of 20 MHz. A Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and Output 0.7V CC 0.3V CC AI00825B Min. Max M45PE40 Unit V °C Unit Unit pF pF 25/35 ...
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... M45PE40 Table 11. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Standby Current I CC1 (Standby and Reset modes) I Deep Power-down Current CC2 Operating Current I CC3 (FAST_READ) I Operating Current (PW) CC4 I Operating Current (SE) CC5 V Input Low Voltage IL V Input High Voltage ...
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... Bytes versus several sequences of only a few Bytes 256) Table 8. and Parameter Min. D.C. D. 0.03 (peak to peak 200 100 (max) C M45PE40 Table 9. Typ. Max. Unit 25 MHz 20 MHz µs 3 µs ...
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... M45PE40 Table 13. AC Characteristics (33MHz operation) 33MHz only available for products marked since week 40 of 2005 Test conditions specified in Symbol Alt. Clock Frequency for the following instructions: FAST_READ, PW, PP PE, SE, DP, RDP, WREN, WRDI, RDSR Clock Frequency for READ f R instructions ...
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... Figure 21. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 22. Write Protect Setup and Hold Timing W tWHSL High Impedance Q tSLCH tCHSH tCHDX tCLCH MSB IN M45PE40 tSHSL tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 29/35 ...
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... M45PE40 Figure 23. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 24. Reset AC Waveforms S Reset 30/35 tCH tCLQV tSHRH tRHSL tRLRH tCL tSHQZ LSB OUT tQLQH tQHQL AI01449D AI06808 ...
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... D1 5.75 D2 3.40 E 5.00 E1 4.75 E2 4.00 e 1. millimeters Min. Max. 1.00 0.00 0.05 0.35 0.48 3.20 3.60 3.80 4.20 0.50 0.75 12° M45PE40 VDFPN-01 inches Typ. Min. 0.0335 0.0394 0.0000 0.0020 0.0256 0.0079 0.0157 0.0138 0.0189 0.2362 0.2264 0.1339 0.1260 0.1417 0.1969 0.1870 0.1575 0.1496 0.1654 0.0500 0.0236 0.0197 0.0295 Max. 12° ...
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... M45PE40 Figure 26. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Package Outline SO-b Note: Drawing is not to scale. Table 15. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Mechanical Data Symbol Typ 0. ...
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... ST Sales Of- fice. M45PE40 – The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M45PE40 T G 33/35 ...
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... M45PE40 REVISION HISTORY Table 17. Document Revision History Date Version 04-Dec-2003 1.2 First public release 23-Jan-2004 2.0 SO16 pin-out corrected Soldering temperature information clarified for RoHS compliant devices. Device grade 31-Mar-2004 3.0 information clarified 05-Aug-2004 4.0 Device grade information further clarified Document promoted to Mature Datasheet. Minor wording changes. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M45PE40 35/35 ...