m45pe40 STMicroelectronics, m45pe40 Datasheet
m45pe40
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m45pe40 Summary of contents
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... Deep Power-down Mode 1µA (typical) More than 100 000 Write cycles More than 20 years’ data retention Packages – ECOPACK® (RoHS compliant) January 2007 VFQFPN8 (MP) 6 × (MLP8) SO8W (MW) 208 mils width SO8N (MN) 150 mils width Rev 7 M45PE40 1/46 www.st.com 1 ...
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... A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Standby Power and Deep Power-Down modes . . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/46 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M45PE40 ...
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... M45PE40 6.4.2 6.5 Read Data Bytes (READ 6.6 Read Data Bytes at Higher Speed (FAST_READ 6.7 Page Write (PW 6.8 Page Program (PP 6.9 Page Erase (PE 6.10 Sector Erase (SE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down (RDP Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Table 17. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4/46 M45PE40 ...
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... M45PE40 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19 Figure 9 ...
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... Description 1 Description The M45PE40 Mbit (512 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle ...
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... Figure 2. VFQFPN and SO connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Section 11: Package mechanical M45PE40 ...
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... This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/46 , causing the first 256 pages of memory to become read-only by protecting M45PE40 ...
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... M45PE40 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/46 ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M45PE40 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... M45PE40 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB ...
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... For optimized timings recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see characteristics (50 MHz 12/46 operation)). M45PE40 PW Page Write (PW) and ...
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... M45PE40 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE40 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M45PE40 5 Memory organization The memory is organized as: 2048 pages (256 bytes each). 524288 bytes (8 bits each) 8 sectors (512 Kbits, 65536 bytes each) Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is Page or Sector Erasable (bits are erased from ...
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... Memory organization Figure 5. Block diagram Reset W Control Logic Address Register and Counter 16/46 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 10000h 00000h 256 Bytes (Page Size) X Decoder M45PE40 Status Register 7FFFFh First 256 Pages can be made read-only 000FFh AI04042B ...
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... M45PE40 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Figure 7. Write Disable (WRDI) instruction sequence 18/46 (Figure 6) sets the Write Enable Latch (WEL) bit Instruction High Impedance AI02281E (Figure 7) resets the Write Enable Latch (WEL) bit Instruction High Impedance AI03750D M45PE40 ...
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... M45PE40 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (13h) ...
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... Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 20/46 Figure Instruction Status Register Out MSB 9. ( WEL Status Register Out MSB M45PE40 b0 (1) WIP 7 AI02031E ...
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... M45PE40 6.5 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... High Impedance Dummy Byte DATA OUT MSB , during the falling edge of Serial Clock (C DATA OUT MSB M45PE40 0 7 MSB AI04006 ...
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... M45PE40 6.7 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Address MSB Data Byte MSB Data Byte MSB Data Byte MSB M45PE40 0 AI04045 ...
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... M45PE40 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Address MSB Data Byte MSB Data Byte MSB Data Byte MSB M45PE40 0 AI04044 ...
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... M45PE40 6.9 Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Figure 15. Sector Erase (SE) instruction sequence Address bits A23 to A19 are Don’t Care. 28/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15 Instruction 23 22 MSB Bit Address AI03751D M45PE40 ) is ...
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... M45PE40 6.11 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. ...
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... Figure 17. Release from Deep Power-down (RDP) instruction sequence 30/46 Figure 17 Instruction High Impedance Deep Power-down Mode M45PE40 , the device is put in the RDP t RDP Standby Mode AI06807 ...
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... M45PE40 7 Power-up and power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included ...
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... These parameters are characterized only, over the temperature range –40°C to +85°C. 32/46 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW threshold WI Parameter M45PE40 Read Access allowed Device fully accessible time Min. Max ...
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... M45PE40 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable Status Register bits are 0. 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied ...
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... Timing Reference Levels 0.8V CC 0.2V CC (1) Parameter Test condition V OUT =25°C and a frequency of 20 MHz. A Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and Output 0.7V CC 0.3V CC AI00825B Min. Max M45PE40 Unit V °C Unit Unit pF pF ...
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... M45PE40 Table 11. DC characteristics Symbol I Input Leakage Current LI I Output Leakage Current LO Standby Current I CC1 (Standby and Reset modes) I Deep Power-down Current CC2 Operating Current I CC3 (FAST_READ) I Operating Current (PW) CC4 I Operating Current (SE) CC5 V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage ...
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... Page Erase Cycle Time Sector Erase Cycle Time (max) C Table 8 and Table 9 Min. Typ. Max. D. 200 100 10.2+ n*0.8/256 1.2 5 0.4+ n*0.8/256 M45PE40 Unit MHz MHz ...
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... M45PE40 Table 13. AC characteristics (33 MHz operation) 33 MHz only available for products marked since week 40 of 2005 Symbol Alt ( CLH ( CLL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL ...
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... Table 8 Parameter (4) (peak to peak) C (2) and Table 9 Min. Typ. Max. D. 100 0 50 100 11 0.8 int(n/8) × 0.025 10 1 M45PE40 Unit 50 MHz 33 MHz µs 30 µs 10 µs 3 µ ...
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... M45PE40 Figure 20. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 21. Write Protect setup and hold timing W tWHSL High Impedance Q Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHSH tCHDX tCLCH MSB IN tCH tCLQV DC and AC parameters tSHSL tSHCH tCHCL ...
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... Value guaranteed by characterization, not 100% tested in production. Figure 23. Reset AC waveforms S Reset 40/46 Test conditions specified in Parameter Conditions Reset Pulse Width Chip should have been Chip Select High to deselected before Reset is Reset High de-asserted tSHRH tRLRH Table 8 and Table 9 Min. Typ. Max tRHSL M45PE40 Unit µs ns AI06808 ...
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... M45PE40 11 Package mechanical Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. Table 16. VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6 × 5 mm, package mechanical data Symbol ...
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... Typ Min Max 2.50 0.00 0.25 1.51 2.00 0.40 0.35 0.51 0.20 0.10 0.35 0.10 6.05 5.02 6.22 7.62 8.89 1.27 – – 0° 10° 0.50 0. 6L_ME inches Typ Min 0.000 0.059 0.016 0.014 0.008 0.004 0.198 0.300 0.050 – 0° 0.020 8 M45PE40 Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 – 10° 0.031 ...
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... M45PE40 Figure 26. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol ccc ccc ...
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... ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 44/46 M45PE40 – (1) M45PE40 ...
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... M45PE40 13 Revision history Table 20. Document revision history Date Version 04-Dec-2003 23-Jan-2004 31-Mar-2004 05-Aug-2004 11-Jan-2005 4-Oct-2005 18-Jan-2007 1.2 First public release 2.0 SO16 pin-out corrected Soldering temperature information clarified for RoHS compliant devices. 3.0 Device grade information clarified 4.0 Device grade information further clarified Document promoted to Mature Datasheet. Minor wording changes. ...
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