CY62127DV30L CYPRESS [Cypress Semiconductor], CY62127DV30L Datasheet
CY62127DV30L
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CY62127DV30L Summary of contents
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... Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O LOW, then data from memory will appear on I/O ...
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... Product Portfolio V Range (V) CC Product Min. Typ. Max. CY62127DV30L 2.2 3.0 3.6 CY62127DV30LL 2.2 3.0 CY62127DV30L 3.6 2.2 3.0 CY62127DV30LL 3.6 CY62127DV30L 2.2 3.0 3.6 CY62127DV30LL [2, 3] Pin Configurations FBGA (Top View BLE I/O A BHE I I/O I I/O I DNU NC I/O I ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ......................................................................... −0.3V to 3.9V DC ...
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Thermal Resistance Parameter Description θ Thermal Resistance (Junction to Ambient) JA θ Thermal Resistance (Junction to Case Test Loads and Waveforms OUTPUT 50 pF INCLUDING JIG AND SCOPE Parameters ...
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... HZCE HZBE HZWE 15. The internal Write time of the memory is defined by the overlap of WE these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05229 Rev. *H ...
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Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [16,17,18] Read Cycle No. 2 (OE Controlled) [14, 15, 19, 20, 21] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE ...
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Switching Waveforms (continued) [14, 15, 19, 20, 21] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE / BLE OE DATA I/O DON'T CARE t HZOE Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE t SA ...
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Switching Waveforms (continued) Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O DON'T CARE Truth Table BHE BLE High High ...
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... Ordering Information Speed (ns) Ordering Code 45 CY62127DV30LL-45BVXI CY62127DV30LL-45ZXI 55 CY62127DV30LL-55BVI CY62127DV30LL-55BVXI CY62127DV30LL-55ZI CY62127DV30L-55ZXI CY62127DV30LL-55ZXI CY62127DV30L-55BVXE CY62127DV30L-55ZSXE 70 CY62127DV30L-70BVI CY62127DV30LL-70BVXI CY62127DV30L-70ZI CY62127DV30LL-70ZXI Please contact your local Cypress sales representative for availability of these parts Package Diagrams TOP VIEW A1 CORNER 6.00± ...
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Package Diagrams (continued) MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05229 Rev. *H ...
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Document History Page Document Title: CY62127DV30 MoBL Document Number: 38-05229 Orig. of REV. ECN NO. Issue Date Change ** 117690 08/27/02 *A 127311 06/13/03 *B 128341 07/22/03 *C 129000 08/29/03 *D 316039 See ECN *E 346982 See ECN *F 369955 ...