W25X64BVSFIG WINBOND [Winbond], W25X64BVSFIG Datasheet
W25X64BVSFIG
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W25X64BVSFIG Summary of contents
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... SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI The W25Q64BV is recommended for all new 64Mb designs. The W25X64BV is available for existing designs that require "25X" device ID for firmware compatibility. W25X64BV Publication Release Date: August 7, 2009 - 1- Preliminary -- Revision B ...
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... Write Enable Latch (WEL) 10.1.3 Block Protect Bits (BP2, BP1, BP0) 10.1.4 Top/Bottom Block Protect (TB) 10.1.5 Reserved Bits 10.1.6 Status Register Protect (SRP) 10.1.7 Status Register Memory Protection 10.2 INSTRUCTIONS 10.2.1 Manufacturer and Device Identification 10.2.2 Instruction Set 10.2.3 Write Enable (06h) 10.2.4 Write Disable (04h) 10.2.5 Read Status Register (05h) ...
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Write Status Register (01h) 10.2.7 Read Data (03h) 10.2.8 Fast Read (0Bh) 10.2.9 Fast Read Dual Output (3Bh) 10.2.10 Page Program (02h) 10.2.11 Sector Erase (20h) 10.2.12 32KB Block Erase (52h) 10.2.13 Block Erase (D8h) 10.2.14 Chip Erase (C7h ...
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... GENERAL DESCRIPTION The W25X64BV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code download applications as well as storing voice, text and data. ...
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PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25X64BV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 8X6-MM Figure 1b. W25X64BV Pad Assignments, 8-pad WSON 8X6-mm (Package Code ZE) 5. PIN DESCRIPTION SOIC 208-MIL, WSON 8X6-MM PIN ...
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PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25X64BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PIN NO. PIN NAME 1 /HOLD 2 VCC 3 N/C 4 N/C 5 N/C 6 N/C 7 /CS 8 ...
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... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bit, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...
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BLOCK DIAGRAM Figure 2. W25X64BV Block Diagram - 8 - W25X64BV ...
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... The W25X64BV supports Dual output operation when using the “Fast Read with Dual Output” (3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for execution ...
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... Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...
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... CONTROL AND STATUS REGISTERS The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, and the state of write protection. The Write Status Register instruction can be used to configure the device write protection features. See Figure 3. ...
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... When the SRP pin is set the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is allowed. 1 0.1.7 Status Register Memory Protection (1) STATUS REGISTER ...
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... Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...
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... A15–A8 A7–A0 dummy A15–A8 A7–A0 (D7–D0) A15–A8 A7–A0 A15–A8 A7–A0 A15–A8 A7–A0 dummy dummy (ID7-ID0) dummy 00h (M7-M0) (ID15-ID8) (ID7-ID0) Memory Capacity Type - 14 - W25X64BV BYTE 6 N-BYTES (2) (Next byte) continuous (Next Byte) (D7–D0) continuous I/O = (one byte (D6,D4,D2,D0) per 4 clocks continuous) (D7,D5,D3,D1) ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip ...
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Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge ...
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... The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table). The Write Status Register instruction also allows the Status Register Protect bit (SRP set ...
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... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in figure 8 ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F eight “dummy” clocks after the 24-bit address as shown in figure 9. The ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO, instead of just DO. This allows data ...
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... Page Program (02h) The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...
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... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Chip Erase (C7h or 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, obtain the devices electronic identification (ID) number or do ...
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Figure 18. Release Power-down / Device ID Instruction Sequence Diagram - 28 - W25X64BV ...
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Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/ Device ID instruction that provides both JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction ...
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... JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 20. For memory type and capacity values refer to Manufacturer and Device Identification table. ...
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ELECTRICAL CHARACTERISTICS 11.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specification for W25X64BV is preliminary. See preliminary designation at the end ...
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Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL t (1) VSL t (1) PUW V (1) WI Figure ...
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DC Electrical Characteristics PARAMETER SYMBOL CONDITIONS Input Capacitance C (1) IN Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature Clock freq. Read Data instruction 03h Clock High, Low Time except Read Data (03h) Clock High, Low Time for Read Data ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Setup Time relative to CLK /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z ...
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Serial Output Timing 11.9 Input Timing 11.10 Hold Timing Publication Release Date: August 7, 2009 - 37 - Preliminary -- Revision B W25X64BV ...
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PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL MIN A 1.75 A1 0.05 A2 1.70 b 0.35 C 0.19 D 5.18 D1 5.13 E 5. 7. 0° θ Notes: ...
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WSON (Package Code ZE) MILLIMETERS SYMBOL MIN A 0.70 A1 0.00 b 0.35 C 0.19 D 7.90 D2 4.60 E 5. 0.45 TYP. MAX MIN 0.75 0.80 0.02755 0.02 0.05 0.0000 0.40 0.48 ...
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SOIC 300-mil (Package Code SF) SYMBOL MIN A 2. 0.33 C 0.18 D 10.08 E 10. 0.38 y θ Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC ...
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... ORDERING INFORMATION W = Winbond 25X = spiFlash Serial Flash Memory with 4KB sectors, Dual Outputs 64B = 64M-bit V = 2. 8-pin SOIC 208-mil SF = 16-pin SOIC 300-mil I = Industrial (-40°C to +85° Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb Notes: 1a. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 1b. The “ ...
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... PACKAGE TYPE DENSITY SS 64M-bit SOIC-8 208mil SF 64M-bit SOIC-16 300mil (1) ZE 64M-bit WSON-8 8x6mm Notes: 1. For WSON packages, the package type ZE is not used in the top side marking. PRODUCT NUMBER W25X64BVSSIG W25X64BVSFIG W25X64BVZEIG - 42 - W25X64BV TOP SIDE MARKING 25X64BVSIG 25X64BVFIG 25X64BVIG ...
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REVISION HISTORY VERSION DATE PAGE A 04/01/09 B 08/07/ 38~42 Preliminary Designation The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not guaranteed. ...