HYB18L512320BF-7.5 QIMONDA [Qimonda AG], HYB18L512320BF-7.5 Datasheet - Page 9

• Manufacturer Part Number: HYB18L512320BF-7.5
• Description: DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.2
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive strength selection for the
DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 1) and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register(BA[1:0] = 10
Rev.1.22, 2007-08
03292006-D7GM-ZBSS
Field
BT
BL
Field
DS
TCSR
PASR
Bits
3
[2:0]
Bits
[6:5]
[4:3]
[2:0]
Type
w
w
Extended Mode Register
Type
w
w
w
Description
Burst Type
0 Sequential
1 Interleaved
Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
Description
Selectable Drive Strength
00
01
Note: All other bit combinations are RESERVED.
Temperature Compensated Self Refresh
Partial Array Self Refresh
000
001
010
101
110
Note: All other bit combinations are RESERVED.
XX Superseded by on-chip temperature sensor (see text)
B
B
B
B
B
B
B
B
)
DS Full Drive Strength
DS Half Drive Strength
PASR all banks (default)
PASR 1/2 array (BA1 = 0)
PASR 1/4 array (BA1 = BA0 = 0)
PASR 1/8 array (BA1 = BA0 = RA12 = 0)
PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
9
Extended Mode Register Definition (BA[1:0] = 10
HY[B/E]18L512320BF-7.5
512-Mbit Mobile-RAM
Internet Data Sheet
TABLE 6
B
)