AT26DF321-S3U ATMEL [ATMEL Corporation], AT26DF321-S3U Datasheet - Page 21

• Manufacturer Part Number: AT26DF321-S3U
• Description: 32-megabit 2.7-volt Only Serial Firmware DataFlash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

10.1.5
10.2
3633C–DFLASH–08/06
Write Status Register
RDY/BSY Bit
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-
mand must have been clocked into the device.
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 10-1. Read Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register
and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-
ter command can be issued, the Write Enable command must have been previously issued to
set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device followed by one byte of data. The one byte of data con-
sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or
Unprotect should be performed, and two additional don’t care bits (see
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global
Protect/Unprotect” section on
The complete one byte of data must be clocked into the device before the CS pin is deasserted;
otherwise, the device will abort the operation, the state of the SPRL bit will not change, no
potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register
will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
SCK
SO
CS
SI
HIGH-IMPEDANCE
MSB
0
0
0
1
0
2
OPCODE
0
3
0
page 14
4
1
5
0
6
1
7
for more details.
MSB
D
STATUS REGISTER DATA
8
D
9
D
10 11
D
AT26DF321 [Preliminary]
D
12
D
13 14
D
D
15 16
MSB
D
STATUS REGISTER DATA
D
17
D
18
D
19
D
20
Table
D
21 22
D
D
23 24
10-2). Any addi-
MSB
D
D
21