W39V040FBP WINBOND [Winbond], W39V040FBP Datasheet
W39V040FBP
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W39V040FBP Summary of contents
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... Operating Mode Selection - FWH Mode...................................................................... 11 8.3 FWH Cycle Definition................................................................................................... 11 9. TABLE OF COMMAND DEFINITION ....................................................................................... 11 9.1 Embedded Programming Algorithm ............................................................................ 12 9.2 Embedded Erase Algorithm......................................................................................... 13 9.3 Embedded #Data Polling Algorithm............................................................................. 14 9.4 Embedded Toggle Bit Algorithm.................................................................................. 15 W39V040FB Data Sheet 512K 8 CMOS FLASH MEMORY WITH FWH INTERFACE Publication Release Date: April 14, 2005 - 1 - Revision A3 ...
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Software Product Identification and Boot Block Lockout Detection Acquisition Flow . 16 10. ELECTRICAL CHARACTERISTICS ......................................................................................... 17 10.1 Absolute Maximum Ratings ......................................................................................... 17 10.2 Programmer interface Mode DC Operating Characteristics........................................ 17 10.3 FWH Interface Mode DC Operating Characteristics ................................................... ...
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... GENERAL DESCRIPTION The W39V040FB is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V040FB results in fast program/erase operations with extremely low current consumption ...
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PIN CONFIGURATIONS Firmware Hub (FWH) Mode A10(FGPI4 R/#C(CLK) 32L STSOP Vpp 9 10 #RESET 11 A9(FGPI3) 12 A8(FGPI2) 13 A7(FGPI1) 14 A6(FGPI0) 15 ...
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FUNCTIONAL DESCRIPTION 6.1 Interface Mode Selection and Description This device can operate in two interface modes, one is Programmer interface mode, and the other is FWH interface mode. The IC (Mode) pin of the device provides the control between ...
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... Program Operation The W39V040FB is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. ...
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During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program ...
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... Command Definition table for detail). 7.3 Block Locking Registers This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These control registers can be set or clear through memory address. Below is the detail description. Please note that this feature is only can be applied on FWH mode. W39V040FB ...
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... Block Locking Registers type and access memory map Table REGISTERS REGISTERS TYPE BLR7 R/W BLR6 R/W BLR5 R/W BLR4 R/W BLR3 R/W BLR2 R/W BLR1 R/W BLR0 R/W Block Locking Register Bits Function Table BIT 7 – 3 Reserved Read Lock 2 1: Prohibit to read in the block where set 0: Normal read operation in the block where clear. This is default state. ...
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Read Lock Any attempt to read the data of read locked block will result in “00H.” The default state of any block is unlocked upon power up. User can clear or set the write lock bit anytime as long ...
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... NO. OF FIELD CLOCKS "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH START 1 Memory Write cycle. 0000b" appears on FWH bus to indicate the initial IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There is always show “0000b” for single byte access. ...
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Embedded Programming Algorithm Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 12 - W39V040FB ...
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Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H Publication Release Date: April 14, 2005 - 13 - ...
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Embedded #Data Polling Algorithm Note Valid address for programming .During a sector erase operation, a valid address is an address within any sector selected for erasure. Start Read Byte (DQ0 - DQ7) Address = SA DQ7 = ...
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Embedded Toggle Bit Algorithm No Note: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Start Read Byte (DQ0-DQ7) Read Byte (DQ0-DQ7) No Toggle Bit =Toggle ? Yes DQ5 = 1 ? Yes Read Byte ...
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Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 Pause 10 S Notes for software product ...
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ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER Operating Temperature Storage Temperature Power Supply Voltage to V Potential SS D.C. Voltage on Any Pin to Ground Potential V Voltage PP Transient Voltage (<20 nS) on Any Pin to Ground Potential ...
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FWH Interface Mode DC Operating Characteristics (V = 3.3V 0.3V 0V PARAMETER SYM. Power Supply Current I CC Read Power Supply Current I CC Program/Erase Standby Current 1 ...
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Programmer Interface Mode AC Characteristics AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load AC Test Load and Waveform D OUT 30 pF (Including Jig and Scope) CONDITIONS ...
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Programmer Interface Mode AC Characteristics, continued 10.7 Read Cycle Timing Parameters (V = 3.3V 0.3V 0V PARAMETER Read Cycle Time Row / Column Address Set Up Time Row / ...
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TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE 11.1 Read Cycle Timing Diagram #RESET T RST A[10:0] R/# #WE #OE High-Z DQ[7:0] 11.2 Write Cycle Timing Diagram T RST #RESET A[10:0] Column Address #OE #WE ...
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Timing Waveforms for Programmer Interface Mode, continued 11.3 Program Cycle Timing Diagram A[10:0] (Internal A[18:0]) 5555 DQ[7: #OE #WE RY/#BY Note: The internal address A[18:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High ...
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Timing Waveforms for Programmer Interface Mode, continued 11.5 Toggle Bit Timing Diagram A[10: #WE #OE DQ6 RY/#BY 11.6 Sector Erase Timing Diagram A[10:0] 5555 (Internal A[18:0]) DQ[7: # #WE SB0 RY/#BY Note: The ...
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FWH INTERFACE MODE AC CHARACTERISTICS 12.1 AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load 12.2 Read/Write Cycle Timing Parameters (V = 3.3V 0.3V 0V ...
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TIMING WAVEFORMS FOR FWH INTERFACE MODE 13.1 Read Cycle Timing Diagram CLK #RESET FWH4 Start FWH IDSEL Read FWH[3:0] XXXXb XA[22]XXb A[18:16] 1101b 0000b 1 Clock 1 Clock Note: When A22 = high, the host ...
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Timing Waveforms, for FWH Interface Mode, continued 13.3 Program Cycle Timing Diagram CLK #RESET FWH4 IDSEL 1st Start XXXXb FWH[3:0 1110b XXXXb ] 0000b 1 Clock 1 Clock CLK #RESET FWH4 2nd Start IDSEL FWH[3:0 XXXXb ] XXXXb 1110b 0000b ...
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Timing Waveforms for FWH Interface Mode, continued 13.4 #DATA Polling Timing Diagram CLK #RESET FWH4 Start IDSEL XXXXb 0000b XXXXb FWH[3:0] 1110b 1 Clock 1 Clock CLK #RESET FWH4 Start IDSEL XXXXb XXXXb 1101b 0000b FWH[3:0] 1 Clock 1 Clock ...
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Timing Waveforms for FWH Interface Mode, continued 13.5 Toggle Bit Timing Diagram CLK #RESET FWH4 Start IDSEL XXXXb XXXXb FWH[3:0] 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 Start IDSEL 0000b FWH[3:0] 1101b XXXXb XXXXb 1 Clock 1 Clock ...
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Timing Waveforms for FWH Interface Mode, continued Sector Erase Timing Diagram CLK #RESET FWH4 1st Start IDSEL FWH[3:0] 0000b 1110b 1 Clock 1 Clock CLK #RESET FWH4 2nd Start IDSEL FWH[3:0] 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 ...
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Timing Waveforms for FWH Interface Mode, continued 13.6 FGPI Register/Product ID Readout Timing Diagram CLK #RESET FWH4 IDSEL Start FWH[3:0] 1101b 0000b A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock Load Address "FFBC0100(hex)" Clocks for GPI Register & "FFBC0000(hex)/FFBC0001(hex) ...
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... TIME PART NO. (nS) W39V040FBP 11 W39V040FBQ 11 W39V040FBPZ 11 W39V040FBQZ 11 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
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PACKAGE DIMENSIONS 16.1 32L PLCC Seating Plane 16.2 32L STSOP θ Symbol A ...
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VERSION HISTORY VERSION DATE A1 August 19, 2004 A2 October 4, 2004 A3 April 14 ,2005 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy ...