ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 29

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

DESIGN EXAMPLE
The external component selection procedure from the Control
Loop Compensation section is used for this design example.
Table 9. 2-Channel, Step-Down DC-to-DC Converter
Requirements
Parameter
Input Voltage, V
Output Voltage for
Output Voltage for
Pulse Skip Feature
CHANNEL 1 CONFIGURATION AND COMPONENTS
SELECTION
Complete the following steps to configure Channel 1:
1.
2.
Channel 1, V
Channel 2, V
For a target output voltage (V
V1SET pin through a 27 kΩ resistor to GND (see Table 4).
Because one of the fixed output voltage options is chosen,
the feedback pin (FB1) must be connected directly to the
output of Channel 1, V
Estimate the duty cycle (D) range. Ideally,
Therefore, for an output voltage of 2.5 V and a nominal
input voltage (V
is 0.5. Using the maximum input voltage (10% greater than
the nominal, or 5.5 V) results in the minimum duty cycle
(D
(10% less than the nominal, or 4.5 V) results in the maximum
duty cycle (D
However, the actual duty cycle will be larger than the
calculated values to compensate for the power losses in the
converter. Therefore, add 5% to 7% to the value calculated
for the maximum load.
Based on the estimated duty cycle range, choose the
switching frequency (f
maximum duty cycle limitations, as shown in Figure 64.
If the input voltage (V
is 2.5 V for Channel 1, choose a switching frequency of
600 kHz with a maximum duty cycle of 0.8. This frequency
option provides the smallest sized solution. If a higher
efficiency is required, choose the 300 kHz option. However,
MIN
D =
) of 0.45, whereas using the minimum input voltage
V
OUT1
OUT2
V
IN
OUT
IN
MAX
IN
) of 0.56.
Specification
5.0 V ±10%
2.5 V, 3 A,
1% V
1.2 V, 3 A,
1% V
Enabled
) of 5.0 V, the nominal duty cycle (D
IN
OUT
OUT
SW
) is 5 V and the output voltage (V
OUT1
) according to the minimum and
p-p ripple
p-p ripple
.
OUT
) of 2.5 V, connect the
Additional
Requirements
None
Maximum load
step: 1.5 A to 3 A,
5% droop maximum
Maximum load
step: 1.5 A to 3 A,
5% droop maximum
None
OUT
NOM
(20)
Rev. 0 | Page 29 of 36
)
)
3.
4.
the actual PCB footprint area of the converter will be larger
because of the bigger inductor and output capacitors.
Select the inductor by using the following equation:
In this equation, V
and f
Therefore, when L = 3.3 μH (the closest minimum
standard value from Table 8) in Equation 5, ΔI
Although the maximum output current required is 3 A,
the maximum peak current is 4.5 A for the current-limit
condition (see Table 7). Therefore, the inductor should be
rated for a peak current of 4.5 A and an average current of
3 A for reliable circuit operation.
Select the output capacitor by using the following equations:
The first equation is based on the output ripple (ΔV
whereas the second equation is based on the transient load
performance requirements that allow, in this case, 5% maxi-
mum deviation. As previously mentioned, perform these
calculations and then choose a capacitor based on the larger
calculated capacitor size.
In this case, the following values are used:
ΔI
f
ΔV
ESR = 3 mΩ (typical for ceramic capacitors)
ΔI
ΔV
Therefore, the output ripple based calculation dictates that
C
dictates that C
the larger capacitor value. As previously mentioned in the
Output Capacitor Selection section, the capacitance value
decreases when dc bias is applied; therefore, select a higher
value. In this case, the next higher value is 69 μF (a 47 μF
capacitor in parallel with 22 μF) with a minimum voltage
rating of 6.3 V.
SW
OUT
L
OUT_STEP
RIPPLE
DROOP
= 600 kHz
= 0.63 A
SW
C
C
L
= 6.2 μF, whereas the transient load based calculation
OUT_MIN
OUT_MIN
=
= 600 kHz, which results in L = 2.32 μH.
= 25 mV (1% of 2.5 V)
= 0.125 V (5% of 2.5 V)
(
V
= 1.5 A
Δ
IN
I
L
−
≅
OUT
≅
×
V
8
ΔI
f
OUT
IN
×
SW
= 60 μF. To meet both requirements, use
OUT_STEP
= 5 V, V
f
SW
)
×
×
V
V
(
ΔV
OUT
IN
×
OUT
⎛
⎜
⎜
⎝
RIPPLE
ΔI
= 2.5 V, ΔI
f
SW
L
−
×
ΔI
ΔV
3
L
DROOP
×
L
ESR
= 0.3 × I
ADP2116
⎞
⎟
⎟
⎠
)
L
= 0.63 A.
L
= 0.9 A,
RIPPLE
),