ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 35

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best
performance from each channel of the ADP2116. Poor circuit
layout degrades the output ripple and regulation, as well as the
EMI and electromagnetic compatibility performance. For
optimum layout, refer to the following guidelines:
•
•
•
•
Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as output
voltage divider components, to analog ground. In addition,
connect the ground references of power components, such as
input and output capacitors, to power ground. Connect
both ground planes to the exposed pad of the ADP2116.
Place the input capacitor of each channel as close to the
VINx pins as possible and connect the other end to the
closest power ground plane.
For low noise and better transient performance, a filter is
recommended between VINx and VDD. Place a 1 μF, 10 Ω
low-pass input filter between the VDD pin and the VINx
pins, as close to the GND pin as possible.
Ensure that the high current loop traces are as short and
as wide as possible. Make the high current path from C
through the L, the C
C
input and output capacitors share a common power ground
plane. In addition, ensure that the high current path from
the PGNDx pin through L and C
ground plane is as short as possible by tying the PGNDx pins
of the ADP2116 to the PGND plane as close as possible to
the input and output capacitors (see Figure 76).
IN
as short as possible. To accomplish this, ensure that the
OUT
, and the power ground plane back to
OUT
back to the power
IN
Rev. 0 | Page 35 of 36
•
•
Connect the ADP2116 exposed pad to a large copper plane
to maximize its power dissipation capability. Thermal
conductivity can be obtained using the method described
in JEDEC Standard JESD51-7.
Place the feedback resistor divider network as close as
possible to the FBx pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the switching
node to avoid noise pickup. To further reduce noise pickup,
place an analog ground plane on either side of the FBx
trace and ensure that the trace is as short as possible to
reduce the parasitic capacitance pickup.
GND
1µF
ADP2116
Figure 76. High Current Traces in the PCB Circuit
VDD
10Ω
PGNDx
VINx
SWx
FBx
C
IN
L
C
V
GND
OUT
IN
V
OUT
ADP2116
LOAD