ADP3168JRUZ-REEL AD [Analog Devices], ADP3168JRUZ-REEL Datasheet - Page 13

• Manufacturer Part Number: ADP3168JRUZ-REEL
• Description: 6-Bit, Programmable 2-, 3-, 4-Phase Synchronous Buck Controller
• Manufacturer: AD [Analog Devices]

APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10 compliant
CPU application are as follows:
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SETTING THE CLOCK FREQUENCY
The ADP3168 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency, f
represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 3 shows that to
achieve an 800 kHz oscillator frequency, the correct value for R
is 249 kΩ. Alternatively, the value for R
where 5.83 pF and 1.5 MΩ are internal IC component values.
For good initial accuracy and frequency stability, a 1% resistor
is recommended.
SOFT START AND CURRENT LIMIT LATCH-OFF
DELAY TIMES
Because the soft-start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C
ramp is generated with a 20 µA internal current source. The
value of R
because it sinks part of the current source to ground. However,
as long as R
The value for C
where t
390 kΩ and a desired a soft-start time of 3 ms, C
Input voltage (V
VID setting voltage (V
Duty cycle (D) = 0.125
Nominal output voltage at no load (V
Nominal output voltage at 65 A load (V
Static output voltage drop based on a 1.3 mΩ load line (R
from no load to full load
(V
Maximum output current (I
Maximum output current step (∆I
Number of phases (n) = 3
Switching frequency per phase (f
C
R
DLY
T
D
SS
) = V
=
is the desired soft-start time. Assuming an R
DLY
=
(
DLY
n
⎛
⎜
⎜
⎝
20
has a second-order impact on the soft-start time
×
ONL
is kept greater than 200 kΩ, this effect is minor.
DLY
µ
f
A
SW
− V
−
can be approximated using
×
2
IN
OFL
×
. 5
V
) = 12 V
VID
R
83
= 1.480 V − 1.3955 V = 84.5 mV
DLY
1
SW,
pF
VID
of each phase to 267 kHz, which
⎞
⎟
⎟
⎠
)
×
) = 1.500 V
−
V
1
t
O
DLY
VID
ss
) = 65 A
5 .
M
1
for the soft-start ramp. This
SW
Ω
O
T
) = 267 kHz
) = 60 A
can be calculated using
ONL
OFL
) = 1.480 V
) = 1.3955 V
DLY
T
). The clock
is 36 nF.
DLY
of
(1)
(2)
Rev. B | Page 13 of 24
O
)
T
The closest standard value for C
chosen, R
time using
If the result for R
should be considered by recalculating the equation for C
longer latch-off time should be used. In no case should R
less than 200 k . In this example, a delay time of 8 ms gives
R
INDUCTOR SELECTION
The choice of inductance for the inductor determines the
ripple current in the inductor. Less inductance leads to more
ripple current, which increases the output ripple voltage and
conduction losses in the MOSFETs but allows using smaller
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses but
requires larger inductors and more output capacitance for the
same peak-to-peak transient deviation. In any multiphase con-
verter, a practical value for the peak-to-peak inductor ripple
current is less than 50% of the maximum dc current in the
same inductor. Equation 4 shows the relationship between
the inductance, oscillator frequency, and peak-to-peak ripple
current in the inductor.
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
Solving Equation 5 for a 10 mV p-p output ripple voltage yields:
If the resulting ripple voltage is less than that designed for, the
inductor can be made smaller until the ripple value is met. This
allows optimal transient response and minimum output
decoupling.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 600 nH inductor is a
good starting point and gives a calculated ripple current of
8.2 A. The inductor should not saturate at the peak current of
25.8 A and should be able to handle the sum of the power
dissipation caused by the average current of 22.7 A in the
winding and core loss.
L
DLY
≥
1
= 402 kΩ. The closest standard 5% value is 390 kΩ.
R
I
L
5 .
R
DLY
≥
=
V
V
DLY
267
V
=
VID
×
VID
. 1
1
can be calculated for the current-limit latch-off
f
96
3 .
×
SW
kHz
×
f
C
SW
m
×
R
(
DLY
DLY
1
×
O
t
Ω
DELAY
−
×
×
L
×
is less than 200 kΩ, a smaller soft-start time
D
×
V
10
(
1
RIPPLE
)
(
1
−
mV
−
(
n
. 0
×
375
D
)
DLY
)
)
=
is 39 nF. Once C
456
nH
ADP3168
DLY
has been
DLY
DLY
(3)
(4)
(5)
, or a
be