ADP3168JRUZ-REEL AD [Analog Devices], ADP3168JRUZ-REEL Datasheet - Page 19

• Manufacturer Part Number: ADP3168JRUZ-REEL
• Description: 6-Bit, Programmable 2-, 3-, 4-Phase Synchronous Buck Controller
• Manufacturer: AD [Analog Devices]

RAMP RESISTOR SELECTION
The ramp resistor (R
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. This expression determines the optimum value:
where A
balancing amplifier gain, R
resistance, and C
closest standard 1% resistor value is 383 kΩ.
The internal ramp voltage magnitude can be calculated using
The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
COMP PIN RAMP
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.
For this example, the overall ramp signal is found to be 0.63 V.
CURRENT-LIMIT SET POINT
To select the current-limit set point, first find the resistor value
for R
with a 3 V source (V
(A
LIM
V
V
V
LIM
). R
R
R
R
R
R
RT
R
R
LIM
. The current limit threshold for the ADP3168 is set
R
=
=
LIM
=
=
=
is the internal ramp amplifier gain, A
383
=
3
3
A
⎛
⎜
⎜
⎝
can be found using the following:
0
R
×
×
R
1
2 .
A
I
×
R
−
5
LIM
A
k
LIM
0
×
×
(
D
×
Ω
n
2 .
1
R
A
(
1
C
×
4
is the internal ramp capacitor value. The
−
×
×
R
×
×
×
2
2 .
−
R
V
D
×
R
f
5
LIM
R
×
R
600
. 0
SW
LIM
) is used for setting the size of the internal
×
DS
m
)
O
L
pF
(
V
1
125
) across R
×
Ω
f
R
−
×
×
SW
V
nH
×
×
n
C
VID
C
DS
)
267
×
5
×
X
R
is the total low-side MOSFET ON
pF
1
D
×
5 .
kHz
)
R
LIM
V
=
O
381
⎞
⎟
⎟
⎠
with a gain of 10.4 mV/µA
k
Ω
D
is the current
(19)
(20)
(21)
(22)
Rev. B | Page 19 of 24
For values of R
be lower than expected, so some adjustment of R
needed. Here, I
the supply. For our example, choosing 120 A for I
R
1% value.
The per-phase current limit described earlier has its limit
determined by the following:
For the ADP3168, the maximum COMP voltage (V
3.3 V, the COMP pin bias voltage (V
current balancing amplifier gain (A
and R
find a per-phase limit of 66 A.
This limit can be adjusted by changing the ramp voltage V
make sure not to set the per-phase limit lower than the average
per-phase current (I
There is also a per-phase initial duty cycle limit determined by
For this example, the maximum duty cycle is found to be 0.42.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3168 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(R
droops in proportion with the load current at any load current
slew rate; this ensures the optimal positioning and allows the
minimization of the output decoupling.
With the multimode feedback structure of the ADP3168, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output
decoupling, meet this goal. There are several poles and zeros
created by the output inductor and decoupling capacitors
(output filter) that need to be compensated for.
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25 to 29 are intended to yield an optimal
starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for the ADP3168).
LIM
O
). With the resistive output impedance, the output voltage
to be 200 kΩ, for which we chose 200 kΩ as the nearest
I
D
DS(MAX)
PHLIM
MAX
=
≅
of 4.2 mΩ (low-side ON resistance at 150°C), we
D
V
LIM
LIM
×
COMP
V
greater than 500 kΩ, the current limit may
is the average current limit for the output of
COMP
A
LIM
(
D
MAX
×
/n).
(
MAX
R
)
V
−
DS
RT
V
)
(
MAX
R
−
V
−
BIAS
V
)
BIAS
D
BIAS
) is 5. Using V
+
) is 1.2 V, and the
I
2
R
LIM
LIM
ADP3168
R
COMP(MAX)
may be
, we find
of 0.63 V
(23)
(24)
R
, but
) is