HIP6019B_05 INTERSIL [Intersil Corporation], HIP6019B_05 Datasheet - Page 8

• Manufacturer Part Number: HIP6019B_05
• Description: Advanced Dual PWM and Dual Linear Power Control
• Manufacturer: INTERSIL [Intersil Corporation]

indicates when C
under-voltage event on either linear output (FB3 or FB4) is
ignored until after the soft-start interval (approximately T3 in
Figure 6). At start-up, this allows V
up over increased time intervals, without generating a fault.
Cycling the bias input voltage (+12V
then on resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper MOSFET (Q1)
causes V
over-voltage threshold of 115% of DACOUT, the over-
voltage comparator trips to set the fault latch and turns Q2
on as required in order to regulate V
DACOUT. This blows the input fuse and reduces V
The fault latch raises the FAULT/RT pin close to VCC
potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on, as
needed to regulate V
Over-Current Protection
All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET’s
on-resistance, r
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB3 and FB4 for under-voltage to protect
against excessive currents.
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the output inductor (L
T1, the OVER-CURRENT2 comparator trips when the voltage
across Q3 (I
R
capacitor (C
LUV
OC1
OC2
OV
SS
OCSET
0.15V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
. This inhibits all outputs, discharges the soft-start
OUT1
+
+
-
-
D
SS
•
) with a 11µA current sink, and increments the
r
to increase. When the output exceeds the
DS(ON)
DS(ON)
CURRENT
SS
UP
LATCH
OVER
S
R
is fully charged (UP signal), such that an
OUT1
Q
) exceeds the level programmed by
to monitor the current for protection
POR
to 1.26V.
8
R
COUNTER
OUT3
IN
OUT1
S
on the VCC pin) off
and V
INHIBIT
to 1.15 x
LATCH
FAULT
S
R
OUT2
OUT1
OUT4
Q
). At time
OUT1
is
to slew
VCC
FAULT
.
HIP6019B
counter. C
with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT/RT pin.
The PWM1 controller and the linear regulator operate in the
same way as PWM2 to over-current faults. Additionally, the
linear regulator and linear controller monitor the feedback
pins for an under-voltage. Should excessive currents cause
FB3 or FB4 to fall below the linear under-voltage threshold,
the LUV signal sets the over-current latch if C
charged. Blanking the LUV signal during the C
interval allows the linear outputs to build above the under-
voltage threshold during normal start-up. Cycling the bias
input power off then on resets the counter and the fault latch.
10V
0A
0V
4V
2V
0V
SS
FIGURE 8. OVER-CURRENT OPERATION
T0
COUNT
recharges at T2 and initiates a soft-start cycle
= 1
T1
OVERLOAD
APPLIED
T2
COUNT
= 2
TIME
REPORTED
FAULT
T3
SS
SS
COUNT
charge
is fully
= 3
T4
April 13, 2005
FN4587.1