HIP6021A_01 INTERSIL [Intersil Corporation], HIP6021A_01 Datasheet - Page 14

• Manufacturer Part Number: HIP6021A_01
• Description: Advanced PWM and Triple Linear Power Controller
• Manufacturer: INTERSIL [Intersil Corporation]

MOSFET Considerations
The HIP6021A requires 5 external transistors. Two
N-Channel MOSFETs are used in the synchronous-rectified
buck topology of PWM1 converter. It is recommended that
the AGP linear regulator pass element be a N-Channel
MOSFET as well. The GTL and memory linear controllers
can also each drive a MOSFET or a NPN bipolar as a pass
transistor. All these transistors should be selected based
upon r
requirements, and thermal management considerations.
PWM MOSFETs
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are dissipated by the HIP6021A and don't
heat the MOSFETs. However, large gate-charge increases
the switching time, t
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The r
the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 10 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and
+12VDC for the bias, the gate-to-source voltage of Q1 is 7V.
The lower gate drive voltage is +12VDC. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage
rating exceeds the maximum voltage applied to VCC.
P
P
UPPER
LOWER
DS(ON)
DS(ON)
=
=
I
----------------------------------------------------------- -
I
-------------------------------------------------------------------------------- -
O
O
is different for the two equations above even if
2
, current gain, saturation voltages, gate supply
2
×
×
r
r
DS ON
DS ON
SW
V
(
(
IN
which increases the upper MOSFET
)
V
)
×
×
IN
V
(
V
OUT
14
IN
–
+
V
I
----------------------------------------------------
OUT
O
×
V
)
IN
×
2
t
SW
×
F
S
HIP6021A
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency could drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.
Linear Controller Transistors
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating VCE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.
P
LINEAR
HIP6021A
-
+
+12V
=
I
O
×
VCC
(
V
GND
IN
UGATE
PHASE
LGATE
PGND
–
V
OUT
)
Q1
Q2
+5V OR LESS
CR1
CC
NOTE:
V
NOTE:
V
DRIVE OPTION
GS
GS
≈
≈
V
V
CC
CC
-5V