MC15XS3400 FREESCALE [Freescale Semiconductor, Inc], MC15XS3400 Datasheet - Page 21

• Manufacturer Part Number: MC15XS3400
• Description: Quad High Side Switch (Quad 15m?)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

low-voltage automotive lighting applications. Its four low
R
55W / 28W bulbs and/or Xenon modules.
using a 16-bit SPI interface. Its output with selectable slew-
rate improves electromagnetic compatibility (EMC) behavior.
OUTPUT CURRENT MONITORING (CSNS)
the designated HS0 : HS3 output or a voltage proportional to
the temperature on the GND flag. That current is fed into a
ground-referenced resistor (4.7kΩ typical) and its voltage is
monitored by an MCU's A/D. The output type is selected via
the SPI. This pin can be tri-stated through the SPI.
DIRECT INPUTS (IN0, IN1, IN2, IN3)
input pins are also used to directly control HS0 : HS3 high side
output pins. If the outputs are controlled by the PWM module,
the external PWM clock is applied to IN0 pin. These pins are
to be driven with CMOS levels, and they have a passive
internal pull-down, R
FAULT STATUS (FS)
external pull-up resistor to V
fault condition is detected, this pin is active LOW. Specific
device diagnostics and faults are reported via the SPI SO pin.
WAKE
protects this pin from high damaging voltages with a series
resistor (10kΩ typ). This input has a passive internal pull-
down, R
RESET (RST)
the device configuration and fault registers, as well as place
the device in a low-current Sleep mode. The pin also starts
the watchdog timer when transitioning from logic [0] to
logic [1]. This pin has a passive internal pull-down, R
CHIP SELECT (CS)
microcontroller (MCU). When this pin is in a logic [0] state,
Analog Integrated Circuit Device Data
Freescale Semiconductor
DS(ON)
The 15XS3400 is one in a family of devices designed for
Programming, control and diagnostics are accomplished
The Current Sense pin provides a current proportional to
Each IN input wakes the device. The IN0 : IN3 high side
This pin is an open drain configured output requiring an
The wake input wakes the device. An internal clamp
The reset input wakes the device. This is used to initialize
The
CS
DWN
MOSFETs (quad 15mΩ) can control four separate
pin enables communication with the master
.
DWN
.
DD
for fault reporting. If a device
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
DWN
INTRODUCTION
.
Additionally, each output has its own parallel input or SPI
control for pulse-width modulation (PWM) control if desired.
The 15XS3400 allows the user to program via the SPI the
fault current trip levels and duration of acceptable lamp
inrush. The device has Fail-safe mode to provide fail-safe
functionality of the outputs in case of MCU damaged.
the device is capable of transferring information to, and
receiving information from, the MCU. The 15XS3400 latches
in data from the input shift registers to the addressed
registers on the rising edge of
information from the power output to the Shift register on the
falling edge of
is logic [0].
state only when SCLK is a logic [0].
pull-up from V
SERIAL CLOCK (SCLK)
15XS3400 device. The serial input (SI) pin accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic low state whenever
makes any transition. For this reason, it is recommended the
SCLK pin be in a logic [0] whenever the device is not
accessed (
pull-down. When
pins are ignored and SO is tri-stated (high-impedance) (see
Figure
down, I
SERIAL INPUT (SI)
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 (MSB) to D0 (LSB). The internal registers of the
15XS3400 are configured and controlled using a 5-bit
addressing scheme described in
addressing and configuration are described in
page 33. SI input has an active internal pull-down, I
DIGITAL DRAIN VOLTAGE (VDD)
power to the SPI circuit. In the event V
the device goes to Fail-safe mode.
The SCLK pin clocks the internal shift registers of the
This is a serial interface (SI) command data input pin.
This pin is an external voltage input pin used to supply
9, page 24). SCLK input has an active internal pull-
DWN
CS
CS
.
DD
CS
logic [1] state). SCLK has an active internal
should transition from a logic [1] to a logic [0]
, I
. The SO output driver is enabled when
CS
UP
.
is logic [1], signals at the SCLK and SI
CS
. The device transfers status
FUNCTIONAL DESCRIPTION
Table
CS
DD
has an active internal
9, page 33. Register
is lost (V
INTRODUCTION
Table
DD
DWN
Failure),
15XS3400
10,
.
CS
CS
21