PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 121
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PIC24FJ128GB
Manufacturer Part Number
PIC24FJ128GB
Description
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24FJ128GB.pdf
(328 pages)
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8.0
The PIC24FJ256GB110 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
8.1
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 7.0
“Oscillator Configuration”.
8.2
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAV instruction is shown in Example 8-1.
EXAMPLE 8-1:
© 2008 Microchip Technology Inc.
PWRSAV
PWRSAV
Note:
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
Instruction-Based Power-Saving
Modes
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
”Section 10. Power-Saving Features”
(DS39698).
#SLEEP_MODE
#IDLE_MODE
Family
PWRSAV INSTRUCTION SYNTAX
Reference
; Put the device into SLEEP mode
; Put the device into IDLE mode
Manual”,
PIC24FJ256GB110 FAMILY
Preliminary
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
8.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption will be reduced
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock will continue to run in Sleep
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may
The device will wake-up from Sleep mode on any of the
these events:
• On any interrupt source that is individually
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
to a minimum provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
mode if the WDT is enabled.
prior to entering Sleep mode.
continue to operate in Sleep mode. This includes
items such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
enabled
Note:
SLEEP MODE
SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
DS39897B-page 119
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