PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 277
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PIC24FJ128GB
Manufacturer Part Number
PIC24FJ128GB
Description
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24FJ128GB.pdf
(328 pages)
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25.2
All PIC24FJ256GB110 family devices power their core
digital logic at a nominal 2.5V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ256GB110 family
incorporate an on-chip regulator that allows the device
to run its core logic from V
The regulator is controlled by the ENVREG pin. Tying V
to the pin enables the regulator, which in turn, provides
power to the core from the other V
ulator is enabled, a low ESR capacitor (such as ceramic)
must
(Figure 25-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
(C
If ENVREG is tied to V
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
V
levels, typically 3.3V. Alternatively, the V
and V
nominal voltage. Refer to Figure 25-1 for possible
configurations.
25.2.1
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.
The regulator can provide this level from a V
2.5V, all the way up to the device’s V
have the capability to boost V
order to prevent “brown out” conditions when the volt-
age drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows V
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect circuit. When V
ating voltage, the circuit sets the Low-Voltage Detect
Interrupt Flag, LVDIF (IFS4<8>). This can be used to
generate an interrupt and put the application into a
low-power operational mode, or trigger an orderly
shutdown.
Low-Voltage Detection is only available when the
regulator is enabled.
© 2008 Microchip Technology Inc.
DDCORE
EFC
) is provided in Section 28.1 “DC Characteristics”.
DD
be
pins can be tied together to operate at a lower
On-Chip Voltage Regulator
DD
/V
CAP
, with a typical voltage drop of 100 mV.
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
connected
pin to run the I/O pins at higher voltage
DD
SS
to
, the regulator is disabled. In
drops below full-speed oper-
DD
.
the
DD
DD
levels below 2.5V. In
V
pins. When the reg-
DDCORE
DDMAX
DDCORE
. It does not
DD
/V
CAP
of about
PIC24FJ256GB110 FAMILY
/V
CAP
Preliminary
pin
DD
FIGURE 25-1:
25.2.2
When the voltage regulator is enabled, it takes approxi-
mately 500 μs for it to generate output. During this time,
designated as T
T
operation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
STARTUP
Note 1:
Regulator Enabled (ENVREG tied to V
Regulator Disabled (ENVREG tied to ground):
Regulator Disabled (V
(10 μF typ)
2.5V
C
2.5V
is applied every time the device resumes
EFC
ON-CHIP REGULATOR AND POR
(1)
These are typical operating voltages. Refer
to Section 28.1 “DC Characteristics” for
the full operating ranges of V
V
(1)
DDCORE
3.3V
STARTUP
3.3V
.
CONNECTIONS FOR THE
ON-CHIP REGULATOR
(1)
V
ENVREG
V
V
, code execution is disabled.
DD
DDCORE
SS
DD
PIC24FJ256GB
V
ENVREG
V
V
V
ENVREG
V
V
DD
DDCORE
SS
DD
DDCORE
SS
tied to V
PIC24FJ256GB
PIC24FJ256GB
/V
CAP
/V
DS39897B-page 275
/V
DDCORE
CAP
CAP
DD
and
DD
):
):
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