DSPIC30F2010 MICROCHIP [Microchip Technology], DSPIC30F2010 Datasheet - Page 21
![no-image](/images/no-image-200.jpg)
DSPIC30F2010
Manufacturer Part Number
DSPIC30F2010
Description
High-Performance, 16-Bit Digital Signal Controllers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.DSPIC30F2010.pdf
(203 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2010-20E/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F2010-20E/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2010-20E/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F2010-20I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F2010-20I/SP
Manufacturer:
MAXIM
Quantity:
6
Part Number:
DSPIC30F2010-20I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F2010-30I/MM
Manufacturer:
VISHAY
Quantity:
30 000
Company:
Part Number:
DSPIC30F2010-30I/MM
Manufacturer:
Microchip Technology
Quantity:
1 863
Part Number:
DSPIC30F2010-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F2010-30I/SOG
Manufacturer:
TOS
Quantity:
453
3.0
3.1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this
group of dsPIC30F devices and is not intended to be
a complete reference source. For more information
on the CPU, peripherals, register descriptions and
general device functionality, refer to the “dsPIC30F
Family Reference Manual” (DS70046). For more
information on the device instruction set and pro-
gramming, refer to the “dsPIC30F/33F
Programmer’s Reference Manual” (DS70157).
Note:
MEMORY ORGANIZATION
Program Address Space
The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
FIGURE 3-1:
Reset -
Alternate Vector Table
Reset - Target Address
Arithmetic Warn. Trap
dsPIC30F2010
Device Configuration
Ext. Osc. Fail Trap
Address Error Trap
Stack Error Trap
Program Memory
(4K instructions)
UNITID (32 instr.)
Data EEPROM
PROGRAM SPACE MEMORY
MAP FOR dsPIC30F2010
Reserved
User Flash
GOTO
DEVID (2)
Reserved
Reserved
Reserved
(Read 0’s)
Vector 52
Vector 53
Reserved
(1 Kbyte)
Reserved
Registers
Vector 0
Vector 1
Reserved
Reserved
Instruction
DS70118G-page 19
000000
000002
000004
000014
00007E
000080
0000FE
000100
001FFE
002000
7FFBFE
7FFC00
7FFFFE
800000
8005BE
8005C0
8005FE
800600
F7FFFE
F80000
F8000E
F80010
FEFFFE
FF0000
FFFFFE
Vector Tables