ATXMEGA256A3B_09 ATMEL [ATMEL Corporation], ATXMEGA256A3B_09 Datasheet - Page 11

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ATXMEGA256A3B_09

Manufacturer Part Number
ATXMEGA256A3B_09
Description
8/16-bit XMEGA A3B Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
7.4.1
7.4.2
7.4.3
8116F–AVR–09/09
I/O Memory
SRAM Data Memory
EEPROM Data Memory
Figure 7-2.
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3B is shown in the
”Peripheral Module Address Map” on page
The XMEGA A3B devices have internal SRAM memory for data storage.
The XMEGA A3B devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
1FFF
5FFF
1000
2000
Data Memory Map (Hexadecimal address)
Internal SRAM
EEPROM
(16 KB)
(4 KB)
56.
XMEGA A3B
11

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