ATXMEGA256A3B_09 ATMEL [ATMEL Corporation], ATXMEGA256A3B_09 Datasheet - Page 44

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ATXMEGA256A3B_09

Manufacturer Part Number
ATXMEGA256A3B_09
Description
8/16-bit XMEGA A3B Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
8116F–AVR–09/09
Figure 25-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each have one ADC. Notation of these peripherals are ADCA and ADCB,
respectively.
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
1-64 X
Reference selection
Configuration
ADC
Trigger
Event
Channel C
Channel D
Channel A
Channel B
XMEGA A3B
Register
Register
Register
Register
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