MN101D07H PANASONIC [Panasonic Semiconductor], MN101D07H Datasheet

MN101D07H

Manufacturer Part Number

MN101D07H

Description

MN101D07G

Manufacturer

PANASONIC [Panasonic Semiconductor]

Datasheet

1.MN101D07H.pdf (5 pages)

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 Interrupts

 Timer Counter

Type

Internal ROM type

ROM (byte)

RAM (byte)

Package (Lead-free)

Minimum Instruction

Execution Time

MN101D07G, MN101D07H

RESET, Runaway, External 0 to 4, key input (P50 to P54), Timer 0 to 4, Timer 6, Timer 7, Capstan FG, Control, HSW,

Cylinder(Drum) FG, Servo V-sync, Synchronous output, OSD, XDS, Serial 0 to 2, A/D (common with PWM 4 reference frequency),

OSD V-sync

Timer counter 0 : 16-bit × 1

Timer counter 1 : 16-bit × 1 (timer function, linear timer counter function)

Timer counter 2 : 16-bit × 1

Timer counter 3 : 16-bit × 1

Timer counter 4 : 16-bit × 1 (timer function, event count [P15 input], generation of serial transmission clock)

Timer counter 5 : 19-bit × 1 (watchdog, stable oscillation waiting function)

Timer counter 6 : 16-bit × 1 (clock function [max. 2 s])

Timer counter 7 : 8-bit × 1 or 4-bit × 2 (timer function, event count)

(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])

(timer function, input capture

(DCTL speciﬁ ed edge), duty judgment of DCTL signal)

(timer function, detection of serial indexing, generation of remote control output carrier frequency)

Clock source ................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overﬂ ow of timer counter 6; 1/512 of XI oscillation

Interrupt source ........... overﬂ ow of timer counter 0

Clock source ................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal

Interrupt source ........... overﬂ ow of timer counter 1

Clock source ................ 1/2, (1/4,) 1/8, (1/16,) 1/12, (1/24) of system clock frequency

Interrupt source ........... overﬂ ow of timer counter 2; input of DCTL speciﬁ ed edge; underﬂ ow of timer 2 shift register 4-bit

Clock source ................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; XI oscillation clock

Interrupt source ........... overﬂ ow of timer counter 3

Clock source ................ 1/8, (1/16) of system clock frequency; external clock input

Interrupt source ........... overﬂ ow of timer counter 4; coincidence of timer counter 4 with OCR4

Clock source ................ system clock

Watchdog interrupt source ... 1/2

Clear by stable oscillation ... after 256 counts by timer counter 5 (218 counts of OSC oscillation clock)

Clock source ................ 1/512 of OSC oscillation clock frequency; XI oscillation clock; 1/4, (1/8,) 1/64, (1/128) of system clock

Interrupt source ........... 1/2

Clock source ................ 1/4, (1/8,) 1/16, (1/32) of system clock frequency; external clock input

Interrupt source ........... overﬂ ow of timer counter 7 (although when 4-bit × 2, there is one interrupt vector. )

71.5 µ s (at 3.0 V to 5.5 V, 14.32 MHz internal frequency di Vision)

clock or OSC oscillation clock frequency

counter; coincidence of timer 2 shift register with timer 2 shift register compare register

frequency

1 6

1 3

, 1/2

MN101D07G

1 9

1 4

, 1/2

of timer counter 5 frequency

128K

0.1397 µ s (at 4.0 V to 5.5 V, 14.32 MHz)

61 µ s (at 2.2 V to 5.5 V, 32.768 kHz)

1 5

overﬂ ow of timer counter 6

[With main clock operated]

[When sub-clock operated]

Mask ROM

LQFP112-P-2020

MN101D07H

160K

61 µ s (at 2.5 V to 5.5 V, 32.768 kHz)

0. 1 397 µ s (at 4.0 V to 5.5 V, 14.32 MHz)

71.5 µ s (at 3.0 V to 5.5 V, 14.32 MHz

internal frequency di Vision)

MN101DF07Z

FLASH

224K

MAD00030GEM

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MN101D07H Summary of contents

Page 1

... MN101D07G, MN101D07H Type Internal ROM type ROM (byte) RAM (byte) Package (Lead-free) Minimum Instruction 71.5 µ s (at 3 5.5 V, 14.32 MHz internal frequency di Vision) Execution Time  Interrupts RESET, Runaway, External key input (P50 to P54), Timer Timer 6, Timer 7, Capstan FG, Control, HSW, Cylinder(Drum) FG, Servo V-sync, Synchronous output, OSD, XDS, Serial A/D (common with PWM 4 reference frequency), OSD V-sync  ...

Page 2

... Clamp method .......................... sync tip clamp, clamp level in 4 levels Output ...................................... composite video output, output of Y/C split video signal, digital output (6 pins) Measure against image ﬂ uctuation ...... built-in AFC circuit Dot clock .................................. 1/2 of OSC oscillation clock (automatic phase adjustment) MAD00030GEM (character types)) video signal) video signal) MN101D07G, MN101D07H ...

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MN101D07H PANASONIC [Panasonic Semiconductor], MN101D07H Datasheet

MN101D07H

Related parts for MN101D07H

MN101D07H Summary of contents

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