STR750F STMICROELECTRONICS [STMicroelectronics], STR750F Datasheet
STR750F
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STR750F Summary of contents
Page 1
... Programmable Analog Watchdog feature – Conversion: min. 3.75 µs, range DD_IO – Start conversion can be triggered by timers ■ 72/38 I/O ports – 72/38 GPIO lines with High Sink capabilities – Atomic bit SET and RES operations Rev 2 STR750F LQFP100 LFBGA100 1.7 mm 1/71 www.st.com 1 ...
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... Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33 Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STR750F ...
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... STR750F 3.3.12 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Contents 3/76 ...
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... UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 38 I/Os 13 Wake-up lines, 11 A/D Channels None USB 3. 3.3V T=LQFP64 10x10, H=LFBGA64 STR750F STR752FRx STR755FVx STR750FVx 16K Table 44) 3 UARTs, 2 SSPs timers 1 PWM timer, 72 I/Os 15 Wake-up lines, 16 A/D Channels CAN None USB+CAN 3 ...
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... Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Enhanced Interrupt Controller (EIC) In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt controller able to handle vectors and 16 priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency. ...
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... Boot from internal SRAM Booting from SMI memory allows booting from a serial flash. This way, a specific boot monitor can be implemented. Alternatively, the STR750F can boot from the internal boot loader that implements a boot from UART. Power Supply Schemes You can connect the device in any of the following ways depending on your application. ...
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... STR750F Low Power modes The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY. ● SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main oscillator can be stopped and the device is driven by a low power clock (f clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator. ● ...
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... The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). 8/71 and detailed in Table 5. This remapping is done by the application via Number of Alternate Function I/Os 100-pin package STR750F 64-pin package Default mapping Remapped ...
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... In LQFP64 devices, CAN and USB cannot be connected simultaneously. Universal Serial Bus (USB) The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL ...
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... PCLK OSC PLL 4M USB Full Speed CAN 2.0B FIFO UART0 2x(16x8bit) FIFO UART1 2x(16x8bit) FIFO UART2 2x(16x8bit) FIFO SSP0 2x(8x16bit) FIFO SSP1 2x(8x16bit) I2C Figure 3. STR750F V DD_IO 18BKP V SS RTC_XT1 RTC_XT2 XT1 XT2 V DDA_PLL V SSA_PLL USBDP USBDM RX, RX,TX,CTS, RTS as AF ...
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... STR750F 2 Pin Description Figure 2. LQFP100 Pinout ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 ADC_IN6 / UART1_RTS / P0.23 TIM2_OC1/ P2.04 UART1_RTS / P2.03 ADC_IN5 / UART1_CTS / P0.22 UART1_TX / P0.21 UART1_RX / P0.20 UART0_RTS / RTCK / P0. A/D input channels = 15 External interrupts / Wake-up Lines TEST SS_IO ...
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... TEST SS_IO_4 LQFP64 9 10 JTMS / P1.19 11 JTCK / P1.18 12 JTDO / P1.17 13 JTDI / P1.16 14 NJTRST STR750F V 48 REG_DIS V 47 SS_IO_2 V 46 SSA_ADC V 45 DDA_ADC V 44 DD_IO_2 P1.03 / TIM2_TI2 43 P0.14 / CAN_RX or USB_DP 42 P0.15 / CAN_TX or USB_DN 41 NRSTIN 40 NRSTOUT 39 XRTC2 38 ...
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... STR750F Table 3. LFBGA100 ball connections P0.03 P1.13 P1.14 B P1.12 P0.02 P0.01 C P0.31 P0. P0.29 P0. P0.28 P0.23 P0.22 F P2.03 P0.21 P0.20 G NJTRST P1.18 P1.19 H P0.13 P1.16 P1.17 J P0.11 P0.12 P1.11 K P0.10 P0.09 P0.08 Table 4. LFBGA64 ball connections 1 A P0.03 B P1.12 C P0.01 D P0.29 E P1.18 F P0.13 G P0.11 H P0. P1.04 P1.06 P1.08 P1.05 P1.07 P1.09 V P1.10 P2.09 DD_IO 18 V P1.01 P1.15 SS_IO SS18 V TEST P1.00 NRSTOUT VREG_DIS NRSTIN SS_IO P2.02 P2.04 P2.05 P2.01 P2.00 P2.07 P2.19 P2.18 P2.17 P0.27 P0.19 P0.26 P0.18 P0.17 P0. P1.04 P1.06 SS_IO V P1.05 P1.07 DD_IO P0.02 P0. P0.28 TEST V SS_IO P1.19 P0.20 P0.21 NJTRST P1.16 P1.17 P0.12 P1.11 P0.19 P0.09 P0.08 P0.17 Pin Description ...
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... OL – O4 MHz on C max drive capability for V OL current on page 54) – O2 MHz on C max drive capability of for V current on page 54) STR750F = 3.3V+/-0.3V or TTL DD_IO means T Table 5 ). =50pF and 8 mA static L =0.4V and for 54) =50pF and 4 mA static L =0.4V (seeOutput driving ...
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... P0.07 (SMI_DOUT) – P0.05 (SMI_CLK) – P0.04 (SMI_CS0) – P0.06 (SMI_DIN) Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected. To avoid excess power consumption, unused I/O ports must be tied to ground. Table 5. STR750F pin description Pin n° Pin Name P1. ADC_IN13 P0. ...
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... Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name P0.29 / TIM1_TI1 ADC_IN8 P0. TIM1_OC1 TEST VSS_IO P0. UART1_RTS / ADC_IN6 P2. TIM2_OC1 P2. UART1_RTS 14 F4 P2.02 P0. UART1_CTS / ADC_IN5 P0. UART1_TX P0. UART1_RX ...
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... STR750F Table 5. STR750F pin description (continued) Pin n° Pin Name P0.11 / UART0_TX / BOOT1 / SMI_CS2 P0. UART0_RX / SMI_CS3 P0.09 / I2C_SDA P0.08 / I2C_SCL 31 H4 P2. P2.18 P2. UART2_RTS P1. /UART0_RTS ADC_IN12 P0. UART2_RTS / ADC_IN7 P0. UART2_CTS P0. UART2_TX P0. UART2_RX P0 ...
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... Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name XT2 XT1 48 J10 31 G6 VSS_IO 49 K10 32 G8 VSSA_PLL 50 J8 P2. P2. V18REG VSS18 VSSBKP V18BKP 56 H10 37 F8 XRTC1 57 G10 38 E8 XRTC2 ...
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... STR750F Table 5. STR750F pin description (continued) Pin n° Pin Name 71 C9 P2.11 72 B10 P2. VSSA_ADC VSS_IO VREG_DIS P0. SMI_DOUT / SSP0_MOSI P0.06 / SMI_DIN SSP0_MISO P0. SSP0_SCLK / SMI_CK P0.04 / SMI_CS0 SSP0_NSS P1. PWM_EMERGE NCY ...
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... Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name 94 D5 P1.01 / TIM0_TI2 P1. TIM0_OC2 V18 VSS18 VSS_IO VDD_IO P0.03 / TIM2_TI1 100 ADC_IN1 1. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO ...
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... STR750F Figure 4. Required external capacitors when regulators are used 97 V SS18 SS18 LFBGA100 18BKP 18 1µF V SSBKP 54 LQFP100 V SS18 53 10 µF V 18REG 52 V DD_IO 44 1 µ 18BKP 18 1µ SSBKP V F8 SS18 10 µF ...
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... FFFF 1 0x2010 0017 Internal Flash 0x2000 0000 0x1FFF FFFF 0 Boot Memory 0x0000 0000 (1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h (2) Only available in STR750Fx2 Reserved 22/71 32K FLASH Memory Space 128/256 Kbytes 0x2010 DFFF SystemMemory 0x2010 C000 0x2010 0017 ...
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... STR750F 3 Electrical parameters 3.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 3.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T selected temperature range) ...
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... Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Pin loading conditions 3.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin input voltage 24/71 STR7 PIN C =50pF L STR7 PIN V IN STR750F Figure 6. Figure 7. ...
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... STR750F 3.1.6 Power Supply Schemes When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below. Power supply scheme 1: Single external 3.3 V power source Figure 8. Power supply scheme 1 V 18_BKP 1µF ...
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... LOW POWER V LPVREG VOLTAGE REGULATOR OFF MAIN V VOLTAGE MVREG REGULATOR V =3.3V IO OUT I/O LOGIC IN 3.3V PLL 3.3V ADC NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON STR750F BACKUP V CIRCUITRY BACKUP (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH KERNEL V CORE (CORE & DIGITAL & MEMORIES) ...
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... STR750F Power supply scheme 3: Single external 5 V power source Figure 10. Power supply scheme 3 V 18_BKP 1µF V SS_BKP VREG_DIS V 18 33nF V SS18 V 18REG 10µF V SS18 V DD_IO 1µF 5.0V +/-0.5V V SS_IO GP I/Os V DD_PLL V SS_PLL V DD_ADC V SS_ADC ADC IN IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON LOW POWER V ~1 ...
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... VOLTAGE REGULATOR OFF MAIN V VOLTAGE MVREG REGULATOR V =5.0V IO OUT I/O LOGIC IN 5.0V PLL 5.0V ADC NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON and Figure 13 STR750F V BACKUP BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS) POWER SWITCH KERNEL V (CORE & CORE DIGITAL & MEMORIES) ...
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... STR750F Figure 12. Power consumption measurements in power scheme 1 (regulators enabled) 3.3V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 13. Power consumption measurements in power scheme 2 (regulators disabled) 3.3V Supply I and I are measured which correspond to: DD_v33 DD_v18 DD_v33 DDA_PLL ...
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... DD_v50 V pins (including DD_v18 1.8V Supply + I DDA_ADC 50 pins ADC pins I DDA_ADC load PLL I DDA_PLL load pins ballast 5.0V I regulator internal 50 transistor load ) 18BKP 1. internal load pins ADC pins I DDA_ADC load PLL I DDA_PLL load pins 5.0V I internal 50 ) 18BKP load 1. internal load STR750F ...
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... STR750F 3.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... Section 3.3.8: I/O port pin characteristics , SS_IO SSA_ADC DDA_ADC maximum is respected maximum IN IN value. A positive INJ(PIN) < Section 3.3.12: 10-bit ADC is the absolute sum of the INJ(PIN) Value -65 to +150 Section 4.2: Thermal characteristics on page 70) STR750F Unit mA ) pins Unit °C ...
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... STR750F 3.3 Operating conditions 3.3.1 General operating conditions Subject to general operating conditions for V Table 9. General operating conditions Symbol f Internal AHB Clock frequency HCLK f Internal APB Clock frequency PCLK Standard Operating Voltage Power Scheme 1 & DD_IO Standard Operating Voltage Power Scheme 3 & 4 Standard Operating Voltage ...
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... V LPVREG 18BKP is observed on the LPVREG 18 18REG , and T A Conditions Min Typ load <150 mA 1.65 1.80 load <10 mA 1.30 1.40 V rise DD_IO 80 slope = 20 µs/V V rise DD_IO 35 slope = 20 ms/V pin and V pins. 18BKP STR750F Max Unit 1.95 V 1.50 V µs ms ...
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... STR750F 3.3.4 Supply current characteristics The current consumption is measured as described in on page 29. Subject to general operating conditions for V Maximum power consumption For the measurements in conditions: ● All I/O pins are configured in output push-pull 0 ● All peripherals are disabled except if explicitly mentioned. ● Embedded Regulators are used to provide 1.8 V (except if explicitly mentioned). ...
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... Figure 12. I DD_V18 I Figure 13. DD_V33 (4) 5V range Figure 10 I DD_V18 I Figure 11 DD_V50 3.3 V range 5V range =3.3V or 5.0V and V =1.8V unless otherwise specified. DD_IO 18 max and V DD_IO STR750F (3) Max (2) Typ 25°C 85°C 105° 117 250 110 <1 3 TBD TBD 15 22 ...
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... STR750F Figure 16. Power consumption in STOP mode in Single supply scheme (3.3 V range) 300 250 TYP (3.3V) MAX (3.6V) 200 150 100 Temp (°C) Figure 18. Power consumption in STANDBY mode (3.3 V range) 30 TYP (3.3V) 25 MAX (3.6V -40 25 Temp (°C) Figure 17. Power consumption in STOP mode 350 ...
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... The RTC is running, clocked by the internal Low Power RC oscillator (LPOSC) ● STANDBY mode is only supported in the single supply scheme (see 38/71 > 32 MHz, burst mode is activated. HCLK 12) 12): and in the dual supply scheme (see Table 14, Table 15 and Table 16. Figure 13). Figure STR750F 12) ...
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... STR750F Subject to general operating conditions for V Table 14. Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes Symbol Para meter Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: f HCLK f HCLK f HCLK f HCLK f HCLK f Supply current in HCLK (4) RUN mode ...
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... A 3.3V (1) Typ 12 130 1950 (6) 630 (6) 2435 I 5 DD_V18 I <1 DD_V33 I 410 DD_V18 I 1475 DD_V33 I 550 DD_V18 I <1 DD_V33 I 910 DD_V18 I 1475 DD_V33 11 14 Section 3.3.4 on page STR750F Table 14. and 5V Unit (2) Typ 15 135 µA 1930 635 2425 5 <1 410 1435 µA 550 1 910 1445 14 µA 18 35. ...
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... STR750F Supply and Clock manager power consumption Table 17. Supply and Clock manager Symbol Parameter Supply current of resonator oscillator I in STOP or WFI mode (LP_PARAM DD(OSC4M) bit: OSC4M ON) FLASH static current consumption in I STOP or WFI mode (LP_PARAM bit DD(FLASH) FLASH ON) Main Voltage Regulator static current ...
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... UART data DD measurement between reset configuration (I2C disabled) and a permanent DD measurement between reset configuration and continuous A/D DD measurement between reset configuration and a running generic HID DD =64 MHz, f =32 MHz, CK_SYS HCLK Typ (3.3V and 5.0V) 0.7 1 1.3 1.6 0.3 (6) 1.2 0.90 2.8 STR750F Unit mA ...
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... STR750F 3.3.5 Clock and timing characteristics XT1 external Clock source Subject to general operating conditions for V Table 19. XT1 external Clock source Symbol External clock source f XT1 frequency XT1 input pin high level V XT1H voltage XT1 input pin low level V XT1L voltage t w(XT1H) XT1 high or low time ...
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... Parameter Conditions see Figure 20 (2) (2) ≤V ≤ DD_I O 90% 10 r(XT1) f(XT1) T XT1 XT2 hi-Z XT1 , and Min Typ Max 32.768 500 0.7xV V DD_IO DD_IO V 0.3xV SS 990 ±1 t w(XT1H) w(XT1L) f OSC4M I L STR750 STR750F Unit kHz V DD_IO ns 5 µA ...
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... STR750F 4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2) The STR750 system clock or the input of the PLL can be supplied by a OSC4M which MHz clock generated from a 4 MHz or 8 MHz crystal or ceramic resonator. If using an 8 MHz oscillator, software set the XTDIV bit to enable a divider by 2 and generate a 4 MHz OSC4M clock ...
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... 5.0 V DD_IO stabilized DD_IO C XRTC1 L1 32 kHz RESONATOR C L2 XRTC2 max ) at the output of the PLL where T min STR750F Min Typ Max 32.768 270 310 370 TBD TBD TBD TBD TBD 160 250 2.5 value FEEDBACK 2 LOOP f ...
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... STR750F difference between N+1 consecutive clock rising edges and T difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. See Figure 23 ● Cycle-to-cycle jitter (N period jitter) This corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs ...
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... V is stable DD_IO MHz PLL_IN V is stable DD_IO MHz PLL_IN V is stable DD_IO : PLL Characteristics on page 46 46. , and T DD_IO Parameter Conditions STR750F . A Value (1) Min Typ Max 4 165 336 960 300 (4) +/-250 (4) +/-2.5 (4) +/-500 for details on how jitter is specified. ...
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... STR750F 3.3.6 Memory characteristics Flash memory Subject to general operating conditions for V otherwise specified. Table 25. Flash memory characteristics Symbol t Word Program PW t Double Word Program PDW t Bank 0 Program (256K) PB0 t Bank 1 Program (16K) PB1 t Sector Erase (64K Sector Erase (8K Bank 0 Erase (256K) ...
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... Fast transient voltage burst limits to be applied V through 100pF on V EFTB a functional disturbance 50/71 Parameter V DD_IO =+25° conforms to IEC 1000-4-2 V DD_IO =+25° and V pins to induce conforms to IEC 1000-4-4 STR750F and DD Level/ Conditions Class =3 =32 MHz Class A CK_SYS =3 =32 MHz Class A CK_SYS ...
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... STR750F Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. ...
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... JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 52/71 Parameter =+25° =+85° =+105° 5 OSC4M =32 MHz CK_SYS Conditions Class Class A =4 MHz, Class A =+25° STR750F (1) ...
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... STR750F 3.3.8 I/O port pin characteristics General characteristics Subject to general operating conditions for V Table 31. General characteristics Symbol V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys hysteresis I Injected Current on any I/O pin INJ(PIN) ΣI Total injected current (sum of all INJ(PIN ...
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... UNUSED I/O PORT UNUSED I/O PORT 10kΩ DD_IO, . can not exceed the absolute maximum rating SS_IO DD_IO STR7XXX STR7XXX Section 3.2.2 : plus the maximum RUN DD_IO, can not exceed the absolute maximum plus the maximum RUN SS_IO and T unless otherwise specified. A STR750F ). OL ...
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... STR750F Table 32. Output driving current I/O Symbol Type Output low level voltage for a standard (1) V I/O pin when 8 pins are sunk at same OL time O2 Output high level voltage for an I/O pin ( when 4 pins are sourced at same time Output low level voltage for a standard (1) V I/O pin when 8 pins are sunk at same ...
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... A Conditions Min Typ Max Unit Between 10% and 90 Between 10% and 90% C =50pF Between 10% and 90% 26. 10% 50% 90% t r(IO)out T (2/3)T and if the duty cycle is (45-55%) STR750F 10 MHz MHz MHz ...
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... STR750F NRSTIN and NRSTOUT pins NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as R NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the ...
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... NRSTIN and NRSTOUT pins on page 58/71 V DD_IO R PU NRSTOUT TO RESET OTHER CHIPS V DD_IO R PU NRSTIN Filter 0.01µF 57. Otherwise the reset will not be taken into account internally. Filter INTERNAL RESET WATCHDOG RESET PULSE SOFTWARE RESET GENERATOR RSM RESET max. level specified in IL(NRSTIN) STR750F STR7X ...
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... STR750F 3.3.9 TB and TIM timer characteristics Subject to general operating conditions for V specified. Refer to Section 3.3.8: I/O port pin characteristics on page 53 input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 35. TB and TIM timers Symbol Parameter Input capture t w(ICAP)in pulse time ...
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... CK_SYS 60 MHz V =3.3 V, Res=16-bits DD_IO V =5.0 V, Res=16-bits DD_IO f =60 MHz CK_TIM CK_TIM CK_SYS 60 MHz : Output speed on page 56. Min Typ Max 1 CK_SYS = (1) 16.6 16 ( 65536 0.0166 1087 65536x 65536 = 71.58 STR750F Unit t CK_TIM ns bit µV µV t CK_TIM µs t CK_TIM s ...
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... STR750F 3.3.10 Communication interface characteristics Inter IC control interface Subject to general operating conditions for V 2 The ST7 I C interface meets the requirements of the Standard I described in the following table with the restriction mentioned below: Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open- ...
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... Measurement points are done at CMOS levels: 0.3xV 62/ bus and timing diagram 4.7kΩ 4.7kΩ 100Ω SDA 100Ω SCL STRT75X t r(SDA su(SDA) h(SDA w(SCKH) w(SCKL) r(SCK) f(SCK) DD REPEATED START t t su(STA) w(STO:STA) STOP t su(STO) and 0.7xV . DD STR750F START ...
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... STR750F 3.3.11 USB characteristics The USB interface is USB-IF certified (Low Speed and High Speed). Table 38. USB characteristics Symbol V Differential Input Sensitivity DI Differential Common Mode V CM Single Ended Receiver Static Output Level Low OL V Static Output Level High OH 1. All the voltages are measured from the local ground potential. ...
Page 64
... PCLK A (1) Min Typ Max 0 SSA_ADC DDA_ADC (2)(3)(4) TBD 3.5 725.25 5802 3.75 30 (11 for sampling + 19 for Successive Approximation) 3.7 =25°C. They are given only as design guidelines frequencies ≤ 8 MHz. ADC STR750F Unit MHz V kΩ pF µA µA µA pF µs 1/f ADC µs 1/f ADC mA ...
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... STR750F ADC Accuracy vs. Negative Injection Current Injecting negative current on specific pins listed in input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed recommended to add a Schottky diode (pin to ground) to pins which may potentially inject negative current. ...
Page 66
... For EMC performance reasons recommended to filter A/D conversion outliers using software filtering techniques. Figure 31. Power supply filtering 66/71 is used as a reference voltage by the A/D converter and DDA_ADC 1 to 10µF 0.1µF STR7 DIGITAL NOISE FILTERING V DD POWER SUPPLY 0.1µF SOURCE (3.3V or 5.0V) EXTERNAL NOISE FILTERING STR750F STR75XX DD_IO V DDA_ADC V SSA_ADC ...
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... STR750F Table 42. ADC accuracy ADC Accuracy with f This assumes that the ADC is calibrated Symbol |E | Total unadjusted error Offset error O E Gain Error Differential linearity error Integral linearity error L 1. Calibration is needed once after each power-up. 2. Refer to ADC Accuracy vs. Negative Injection Current on page 65 3 ...
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... Figure 33. 64-Pin Low Profile Quad Flat Package (10x10) Figure 34. 100-Pin Low Profile Flat Package (14x14) 68/ STR750F mm inches Dim. Min Typ Max Min Typ 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c ...
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... STR750F Figure 35. 64-Low Profile Fine Pitch Ball Grid Array Package Figure 36. 100-Low Profile Fine Pitch Ball Grid Array Package Figure 37. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print ...
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... On the other hand, I/O INT and ( (at equilibrium) for a known T D may be obtained by solving equations (1) and (2) iteratively for any Parameter + P ), INT I/O ( neglected) is given by: I/O Using this value of K, the values A. Value STR750F Unit °C/W °C/W °C/W °C/W ...
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... STR750F 5 Order codes Table 44. Order codes Partnumber STR750FV0T6 STR750FV1T6 STR750FV2T6 STR750FV2H6 STR751FR0T6 STR751FR1T6 STR751FR2T6 STR751FR2H6 STR752FR0T6 STR752FR1T6 STR752FR2T6 STR752FR2H6 STR752FR0T7 STR752FR1T7 STR752FR2T7 STR752FR2H7 STR755FR0T6 STR755FR1T6 STR755FR2T6 STR755FR2H6 STR755FV0T6 STR755FV1T6 STR755FV2T6 STR755FV2H6 1. For other memory sizes, contact sales office. Flash Prog. Memory ...
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... Revision history 6 Revision history Table 45. Revision history Date Revision 25-Sep-2006 30-Oct-2006 72/71 Description of Changes 1 Initial release 2 Added power consumption data for 5V operation in STR750F Section 3 ...
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... STR750F Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...